Editing SAA-001

Jump to navigation Jump to search
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then publish the changes below to finish undoing the edit.

Latest revision Your text
Line 1: Line 1:
* Seen in [[CUH-10xx series]]
{{Wikify}}
* Productcode: 1-889-352-11 or 1-889-352-21


= Gallery =
== SKU differentiation ==
* [[CUH-10xx series]] contain [[SAA-001]] board.


productcode: [[1-889-352-11]] or [[1-889-352-21]]
=== Gallery ===
<gallery>
<gallery>
File:SAA001-backside.jpg|[[SAA-001]] - backside
File:SAA001-backside.jpg|[[SAA-001]] - backside
Line 26: Line 29:
File:SAA-001 - Backside - IMG 2992.JPG|[[SAA-001]] backside - image2992
File:SAA-001 - Backside - IMG 2992.JPG|[[SAA-001]] backside - image2992
File:SAA-001 - Backside - IMG 2993.JPG|[[SAA-001]] backside - image2993
File:SAA-001 - Backside - IMG 2993.JPG|[[SAA-001]] backside - image2993
File:SAA-001 - Backside - IMG 2993.JPG|[[SAA-001]] backside - image2994
File:SAA-001 - Backside - IMG 2994.JPG|[[SAA-001]] backside - image2994
File:SAA-001 - Backside - IMG 2995.JPG|[[SAA-001]] backside - image2995
File:SAA-001 - Backside - IMG 2995.JPG|[[SAA-001]] backside - image2995
File:SAA-001 - Backside - IMG 2996.JPG|[[SAA-001]] backside - image2996
File:SAA-001 - Backside - IMG 2996.JPG|[[SAA-001]] backside - image2996
Line 33: Line 36:
</gallery>
</gallery>


= Components =
{| class="wikitable sortable"
|-
! Component !! Package
|-
| APU || [[CXD90026G]]
|-
| APU RAM || [[K4G41325FC-HC03]]
|-
| Southbridge || [[CXD90025G]]
|-
| Southbridge RAM || [[K4B2G1646E-BCK0]]
|-
| Serial Flash || [[MX25L25635FMI-10G]]
|-
| Syscon || [[A01-COL]]
|-
| SATA || [[MB86C311B]]
|-
| HDMI || [[MN86471A]]
|-
| LAN || [[88EC060-NN82]]
|-
| Wireless communication module || [[88W8797]]
|-
| BD-ROM || [[R8J32841FP1]]
|-
| USB 3.0 Hub || [[GL3520]]
|}
== Notes on components ==


* APU to MC link is PCI-e Gen2 (5Gbit/s, 4 lanes)
=== Notes on Components ===
<SoC> Some extra info:
* APU to MC link is indeed PCI-e Gen2 (5Gbit/s, 4 lanes)
* APU to BD-ROM is SATA I (1.5 Gbit/s)
* APU to BD-ROM is SATA I (1.5 Gbit/s)
* DDR3 bootup speed is 400MHz (DDR3-800, that is very low because DDR3 chip is rated for DDR3-1600). Not sure if DDR3 would go higher on fully booted unit).
* DDR3 bootup speed is 400MHz (DDR3-800, that's very low because DDR chip is rated for DDR3-1600). Not sure if DDR3 would go higher on fully booted unit).
* unit denies to boot if I cut some of PCI-e lanes. Normally, x4 PCI-e interface would work on x1 lane without any problem (with lower bandwidth), but PS4 LED flashes blue forever if I cut PCI-e down to 1 lane.
* unit denies to boot if I cut some of PCI-e lanes. Normally, x4 PCI-e interface would work on x1 lane w/o problems (with lower bandwidth), but PS4 flashes blue forever if I cut PCI-e down to 1 lane.
 
= X-ray Silicon Pron =
 
https://siliconpr0n.org/map/sony/saa-001/x-ray/
 


{{Components}}
{{Components}}
<noinclude>[[Category:Main]]</noinclude>
<noinclude>[[Category:Main]]</noinclude>
Please note that all contributions to PS4 Developer wiki are considered to be released under the GNU Free Documentation License 1.2 (see PS4 Developer wiki:Copyrights for details). If you do not want your writing to be edited mercilessly and redistributed at will, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource. Do not submit copyrighted work without permission!

To protect the wiki against automated edit spam, we kindly ask you to solve the following hCaptcha:

Cancel Editing help (opens in new window)

Templates used on this page:

Retrieved from "http://www.psdevwiki.com/ps4/SAA-001"