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AMD System Management Unit (SMU) is a thermal and electric management unit found in modern AMD x86 processors. AMD SMU must not be mistaken with AMD SAMU (the Secure Asset/Access Management Unit), a separate processor that handles lots of the encryption/decryption tasks on the PS4.
AMD SMU must not be mistaken with AMD SAMU.


See also the [https://psdevwiki.com/ps5/Devices#System_Management_Unit_.28SMU.29_.28MP1.29 PS5 AMD SMU].
= PS4 AMD SMU Hashes =
 
The AMD System Management Unit (SMU) is a subcomponent of the Northbridge that is responsible for a variety of system and power management tasks during boot and
runtime. The SMU contains a microcontroller to assist... As the Northbridge is part of the CPU, the SMU is a processor inside a processor (or SoC) so it was named Matroshka processor by Rudolf Marek.
 
The system management unit (SMU) is tasked with the job of continuously sampling sensory data and making rapid corrections to various circuits on the chip. One such example is the control of the boost circuit. Additional tasks include voltage level control which is supplied as targets to the power supply monitors (PSMs), C-state boosts, thermal management ensuring the chip does not exceed the specifications temperatures, and electrical design current management which ensures the current draw does not exceed the specifications of the external voltage rails.
 
See the [https://media.ccc.de/v/31c3_-_6103_-_en_-_saal_2_-_201412272145_-_amd_x86_smu_firmware_analysis_-_rudolf_marek video of Rudolf Marek explaining AMD x86 SMU firmware analysis at 31C3]. See also his [https://fahrplan.events.ccc.de/congress/2014/Fahrplan/system/attachments/2503/original/ccc-final.pdf slides].
 
= PS4 AMD SMU revision =
 
Despite continuing claims from some that the PS4 SoC must contain a higher-end Kaveri/Steamroller-class CPU, the tiny x86 cores implemented here are clearly based on Jaguar/Kabini. Each core is roughly 3.1 millimeters square - exactly the size AMD gave for that chip. The large (rather plaid) boxes in each quad-core arrangement are the L2 cache. Memory I/O wraps all three sides of the die, which makes sense - the SoC itself uses a GPU-style memory layout. It is not clear from this diagram whether HSA is implemented on the chip or not, though it might be possible to identify the IOMMU unit that HSA requires with a close analysis.
 
* See [https://www.extremetech.com/gaming/171375-reverse-engineered-ps4-apu-reveals-the-consoles-real-cpu-and-gpu-specs].
* See [https://en.wikipedia.org/wiki/List_of_AMD_processors_with_3D_graphics#%22Kabini%22_(2013,_SoC)_2 Kabini] and [https://en.wikipedia.org/wiki/Jaguar_(microarchitecture) Jaguar].
 
= PS4 AMD SMU firmware =
 
In the PS4 BIOS, there is the AMD Generic Encapsulated Software Architecture (AGESA) firmware, which contains all AMD silicon initialization including the SMU firmware.
 
= PS4 AMD SMU HMAC-SHA1 Hashes =
 
Remind that HMAC-SHA1 digests are 20-byte long.


<pre>
<pre>
1.00 -> 1.02:
1.00 -> 1.02 :
(ES32)
(ES32)
0xb92864eb
0xb92864eb
Line 34: Line 12:
0x3ad5b9ed
0x3ad5b9ed


1.03 -> 2.04:
1.03 -> 2.04 :
 
(ES32)
(ES32)
0xa372c000
0xa372c000
Line 42: Line 21:
0xce341069
0xce341069


2.50 -> ?.??:
2.50 -> ???
(ES32) (key maybe changed as this hash is not confirmed)
(ES32) (Maybe key changed, this hash is not confirmed)
0xa11c2a0f
0xa11c2a0f
0x550ae4ec
0x550ae4ec
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