Talk:RAM: Difference between revisions

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== Main System Memory ==
source: http://www.edepot.com/playstation3.html#PS3_Motherboard


The PS3 has 256MB of 64 bit bus Rambus XDR main system memory. Some models use four 64MB Samsung chips, while other models uses four 64MB Elpida chips. Note that another 256MB of GDDR3 memory is located inside the RSX chip using four 64MB Samsung chips. The earlier models with hardware PS2 compatibility also contained an extra 32MB of RDRAM using two 16MB Samsung chips.
== Direct Rambus Technology ==


A sample of the Memory chips in different PS3 models:
A PDF from Stanford explains this very well.
{| border="1" cellspacing="0" cellpadding="5" border="#999" class="wikitable" style="border:1px solid #999; border-collapse: collapse;"
|- bgcolor="#cccccc"
! Type !! Size !! Speed !! Voltage !! Packaging !! Manufacturer !! Serial Number !! Description
|-
| Rambus XDR || 64MB || 400MHz ||  ||  || Elpida || EDX5116ACSE-3C-E || 256MB total (4 chips) for PS3 System Memory (Initial Models)
|-
| Rambus XDR || 64MB || 400MHz ||  ||  || Samsung || K4Y50164UC-JCB3 || 256MB total (4 chips) for PS3 System Memory (Initial Models)
|-
| Rambus XDR || 64MB || 400MHz ||  ||  || Samsung || K4Y50164UE-JCB3 || 256MB total (4 chips) for PS3 System Memory (CECHG,CECHK)
|-
| Rambus XDR || 64MB || 400MHz ||  ||  || Elpida || X5116ADSE-3C-E || 256MB total (4 chips) for PS3 System Memory (CECH-20xx)
|-
| Rambus XDR || 128MB || 400MHz ||  ||  || Elpida || X1032BASE-3C-F || 256MB total (2 chips) for PS3 System Memory (CECH-21xx and later)
|-
|}
:


[http://www.stanford.edu/class/ee382/MISC/rambus.pdf Direct Rambus Technology]


== Graphics Memory ==
== K4Y50164UE-JCB3 Datasheet ==
{| border="1" cellspacing="0" cellpadding="5" border="#999" class="wikitable" style="border:1px solid #999; border-collapse: collapse;"
|- bgcolor="#cccccc"
! Type !! Size !! Speed !! Voltage !! Packaging !! Manufacturer !! Serial Number !! Description
|-
| GDDR3 || 64MB || 700MHz ||  ||  || Samsung || K4J52324QC-SC14 || 256MB total (4 chips) for PS3 Graphics Memory
|-
|}
:


A very helpful PDF explaining everything there is to know about this chip.


== PS2 Compatibility Memory ==
http://www.keepandshare.com/doc/4521123/k4y50044ue-pdf-3-5-meg?da=y
{| border="1" cellspacing="0" cellpadding="5" border="#999" class="wikitable" style="border:1px solid #999; border-collapse: collapse;"
|- bgcolor="#cccccc"
! Type !! Size !! Speed !! Voltage !! Packaging !! Manufacturer !! Serial Number !! Description
|-
| RDRAM || 16MB || 800MHz ||  || 54-pin || Samsung || K4R271669F || 32MB total (2 chips) for Hardware PS2 Compatibility System Memory
|-
|}
:
 
source: http://www.edepot.com/playstation3.html#PS3_Motherboard


todo: add datasheet links, more package & pad/pin info, cleanup
== Backdoor? ==
According to a tweet by (already deleted, [https://twitter.com/RichDevX/status/504389462496137217 source]), there is a backdoor in XDR Ram that allows the attacker to write to any place in the memory. 16:40, 27 August 2014‎ [[User:Zecoxao]]
: without actual tweet hard to discuss... It is in the nature of /XDR/ RAM to be Random Accessable Memory in the first place ;) As long as you stick to that one module at a time. There is no HV/W^X etc on that hardware level (which takes place in the CPU / OS instead) [[User:Euss|Euss]] ([[User talk:Euss|talk]]) 12:13, 27 August 2014 (EDT)
:: sorry about that, should've taken a picture :P i'm not as fast as you when you're awake :) 17:36, 27 August 2014 [[User:Zecoxao]]
::: According to wikipedia: each chip has a low-speed serial bus used to determine its capabilities and configure its interface. This consists of three shared inputs: a reset line (RST), a serial command input (CMD) and a serial clock (SCK), and serial data in/out lines (SDI and SDO) that are daisy-chained together and eventually connect to a single pin on the memory controller. [http://en.wikipedia.org/wiki/XDR_DRAM#Protocol Source] 19:25, 27 August 2014 [[User:NiceShot]]

Latest revision as of 22:17, 27 August 2014

source: http://www.edepot.com/playstation3.html#PS3_Motherboard

Direct Rambus Technology[edit source]

A PDF from Stanford explains this very well.

Direct Rambus Technology

K4Y50164UE-JCB3 Datasheet[edit source]

A very helpful PDF explaining everything there is to know about this chip.

http://www.keepandshare.com/doc/4521123/k4y50044ue-pdf-3-5-meg?da=y

Backdoor?[edit source]

According to a tweet by (already deleted, source), there is a backdoor in XDR Ram that allows the attacker to write to any place in the memory. 16:40, 27 August 2014‎ User:Zecoxao

without actual tweet hard to discuss... It is in the nature of /XDR/ RAM to be Random Accessable Memory in the first place ;) As long as you stick to that one module at a time. There is no HV/W^X etc on that hardware level (which takes place in the CPU / OS instead) Euss (talk) 12:13, 27 August 2014 (EDT)
sorry about that, should've taken a picture :P i'm not as fast as you when you're awake :) 17:36, 27 August 2014 User:Zecoxao
According to wikipedia: each chip has a low-speed serial bus used to determine its capabilities and configure its interface. This consists of three shared inputs: a reset line (RST), a serial command input (CMD) and a serial clock (SCK), and serial data in/out lines (SDI and SDO) that are daisy-chained together and eventually connect to a single pin on the memory controller. Source 19:25, 27 August 2014 User:NiceShot
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