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• Template talk:Syscon pinout BGA 200 pads
  T4 XTAL / T5 EXTAL goes to [X4001] of 16.9344 MHz
  4 KB (561 words) - 03:54, 26 June 2021
• EBUS
  | 50 || JL9350 || D4 || SB_EBUS_DATA4 (EBUSDATA[4] / T5) || SB_EBUS_DATA4 (EBUSDATA[4] / AE25) || SB_EBUS_DATA4 (EBUSDATA[4] / M27)
  11 KB (1,424 words) - 15:11, 14 August 2021
• CXD2984GB
  | T5 || ||
  23 KB (2,836 words) - 22:07, 6 June 2022
• PS2 Official Configs
  0xFFFA0,0, 0x00A0682D 2D 68 A0 00 dmove t5,a1 0xFFFA4,0, 0x8DAE0014 14 00 AE 8D lw t6,0x14(t5)
  105 KB (12,414 words) - 00:54, 26 May 2024
• CXD9963GB
  | data-sort-value="0T05" | T5 || || || ||
  42 KB (4,184 words) - 15:18, 19 November 2022
• PS2 Custom Configs
  0x05A00022 bltz t5,0x4558A4 -> 0x10000022 b 0x4558A4 0x05A00022 bltz t5,0x358AB0 -> 0x10000022 b 0x358AB0
  38 KB (4,957 words) - 06:56, 25 September 2022
• User talk:Roxanne
  0xFFFA0,0, 0x00A0682D 2D 68 A0 00 dmove t5,a1 0xFFFA4,0, 0x8DAE0014 14 00 AE 8D lw t6,0x14(t5)
  138 KB (17,850 words) - 21:51, 27 June 2024
• Template:Syscon pinout BGA 200 pads
  | data-sort-value="T05" | T5 || data-sort-value="ZC" | <abbr title="Reset & Clock">CLK</abbr> || EXTAL |
  50 KB (6,366 words) - 03:43, 16 November 2022
• Template:RSX pad layout 41x41
  | T5 || ||
  44 KB (5,008 words) - 17:08, 30 September 2022
• Keys
  == T5 ==
  121 KB (21,370 words) - 00:42, 24 June 2024
• Template:CELL pad layout 45nm v1
  | data-sort-value="0T05" | T5 || || || ||
  72 KB (5,997 words) - 05:38, 16 November 2022
• Template:CELL pad layout 45nm v2
  | data-sort-value="0T05" | T5 || || || ||
  74 KB (6,188 words) - 05:39, 16 November 2022
• Template:CELL pad layout 65nm
  | data-sort-value="0T05" | T5 || || || ||
  73 KB (6,284 words) - 05:37, 16 November 2022
• Template:CELL pad layout 90nm
  | data-sort-value="0T05" | T5 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND"
  351 KB (42,654 words) - 05:34, 16 November 2022