PCI

File:PCI pads - as seen on COK-002
note: Two circular pads in the bottom right corner are for southbridge serial

PCI

Bus, resembling Conentional PCI 2.3, directly connected to South Bridge, with 80 exposed pads

80 pin miniPCI pad layout

CN3208 80P

80P Pin	Usage	100P Pin	124P Pin	Remark
01	+3.3V_PCI	03, 08, 12, 15, 24, 47, 54, 72, 73	19, 24, 28, 31, 40, 63, 70, 88, 89 (not 124)	VCC
02	GND	7, 11, 16, 21, 33, 34, 39, 46, 53, 58, 61, 66, 67, 85, 86, 98	23, 27, 32, 37, 49, 50, 55, 62, 69, 74, 77, 82, 83, 101, 102, 114	Ground
03	PIO15			?
04	PIO11			?
05	PIO14			?
06	PIO10			?
07	PIO13			?
08	PIO9			?
09	PIO12			?
10	PIO8			?
11	GND	07, 11, 16, 21, 33, 34, 39, 46, 53, 58, 61, 66, 67, 85, 86, 98	23, 27, 32, 37, 49, 50, 55, 62, 69, 74, 77, 82, 83, 101, 102, 114	Ground
12	GND	07, 11, 16, 21, 33, 34, 39, 46, 53, 58, 61, 66, 67, 85, 86, 98	23, 27, 32, 37, 49, 50, 55, 62, 69, 74, 77, 82, 83, 101, 102, 114	Ground
13	/INTA	04	20	Interrupt line A (open-drain)
14	/INTB	01	17	Interrupt line B (open-drain)
15	/INTC	-	-	Interrupt line C (open-drain)
16	/INTD	-	-	Interrupt line D (open-drain)
17	/RST	10	26	Reset
18	GND	07, 11, 16, 21, 33, 34, 39, 46, 53, 58, 61, 66, 67, 85, 86, 98	23, 27, 32, 37, 49, 50, 55, 62, 69, 74, 77, 82, 83, 101, 102, 114	Ground
19	/GNT	14	30	Bus grant from motherboard to card
20	CLK	09	25
21	GND	07, 11, 16, 21, 33, 34, 39, 46, 53, 58, 61, 66, 67, 85, 86, 98	23, 27, 32, 37, 49, 50, 55, 62, 69, 74, 77, 82, 83, 101, 102, 114	Ground
22	GND	07, 11, 16, 21, 33, 34, 39, 46, 53, 58, 61, 66, 67, 85, 86, 98	23, 27, 32, 37, 49, 50, 55, 62, 69, 74, 77, 82, 83, 101, 102, 114	Ground
23	/PME	18	34	Power management event. 3.3 V, open drain, active low
24	/REQ			Bus request from card to motherboard
25	AD30	22	38	Address/Data 30
26	AD31	17	33	Address/Data 31
27	AD28	26	42	Address/Data 28
28	AD29	19	35	Address/Data 29
29	AD26	28	44	Address/Data 26
30	AD27	23	39	Address/Data 27
31	AD24	30	46	Address/Data 24
32	AD25	25	41	Address/Data 25
33	IDSEL			IDSEL is asserted by PCI system to select the connected device during configuration read and write transactions.
34	/C/BE3			Command/Byte Enable 3 // These inputs are the multiplexed Bus Command and Byte Enable signals on the PCI bus.
35	GND	07, 11, 16, 21, 33, 34, 39, 46, 53, 58, 61, 66, 67, 85, 86, 98	23, 27, 32, 37, 49, 50, 55, 62, 69, 74, 77, 82, 83, 101, 102, 114	Ground
36	GND	07, 11, 16, 21, 33, 34, 39, 46, 53, 58, 61, 66, 67, 85, 86, 98	23, 27, 32, 37, 49, 50, 55, 62, 69, 74, 77, 82, 83, 101, 102, 114	Ground
37	AD22	36	52	Address/Data 22
38	AD23	31	47	Address/Data 23
39	AD20	38	54	Address/Data 20
40	AD21	35	51	Address/Data 21
41	AD18	42	58	Address/Data 18
42	AD19	37	53	Address/Data 19
43	AD16	44	60	Address/Data 16
44	AD17	41	57	Address/Data 17
45	/FRAME	48	64	FRAME is driven by the current master to indicate the beginning and duration of an access. While FRAME is asserted, data transaction continues. When FRAME is deasserted, the transaction is in the final data phase.
46	/C/BE2	43	59	Command/Byte Enable 3 // These inputs are the multiplexed Bus Command and Byte Enable signals on the PCI bus.
47	GND	07, 11, 16, 21, 33, 34, 39, 46, 53, 58, 61, 66, 67, 85, 86, 98	23, 27, 32, 37, 49, 50, 55, 62, 69, 74, 77, 82, 83, 101, 102, 114	Ground
48	GND	07, 11, 16, 21, 33, 34, 39, 46, 53, 58, 61, 66, 67, 85, 86, 98	23, 27, 32, 37, 49, 50, 55, 62, 69, 74, 77, 82, 83, 101, 102, 114	Ground
49	/TRDY	50	66	TRDY indicates the PCI bus slave can complete the current data phase of the transaction.
50	/IORDY	45	61	IRDY indicates the PCI bus master can complete the current data phase of the transaction.
51	/STOP	52	68	STOP indicates the connected device is requesting that the current master stop the current transaction.
52	/DEVSEL	56	72	The connected device drives this signal active to indicate that it has decoded its address as the target of the current access.
53	PAR	40	56	The connected device drives PAR in read data phases for parity checking.
54	/PERR	55	71	The PERR pin reports data parity errors during data read phases. Even parity over AD[31:00] and C/BE[3:0]#
55	AD15	60	76	Address/Data 15
56	/SERR	51	67	System error
57	AD13	62	78	Address/Data 13
58	/C/BE1	57	73	Command/Byte Enable 1 // These inputs are the multiplexed Bus Command and Byte Enable signals on the PCI bus.
59	AD11	64	80	Address/Data 11
60	AD14	59	75	Address/Data 14
61	GND	07, 11, 16, 21, 33, 34, 39, 46, 53, 58, 61, 66, 67, 85, 86, 98	23, 27, 32, 37, 49, 50, 55, 62, 69, 74, 77, 82, 83, 101, 102, 114	Ground
62	GND	07, 11, 16, 21, 33, 34, 39, 46, 53, 58, 61, 66, 67, 85, 86, 98	23, 27, 32, 37, 49, 50, 55, 62, 69, 74, 77, 82, 83, 101, 102, 114	Ground
63	AD09	68	84	Address/Data 09
64	AD12	63	79	Address/Data 12
65	/C/BE0	70	86	Command/Byte Enable 0 // These inputs are the multiplexed Bus Command and Byte Enable signals on the PCI bus.
66	AD10	65	81	Address/Data 10
67	AD06	74	90	Address/Data 06
68	AD08	69	85	Address/Data 08
69	AD04	76	92	Address/Data 04
70	AD07	71	87	Address/Data 07
71	GND	07, 11, 16, 21, 33, 34, 39, 46, 53, 58, 61, 66, 67, 85, 86, 98	23, 27, 32, 37, 49, 50, 55, 62, 69, 74, 77, 82, 83, 101, 102, 114	Ground
72	GND	07, 11, 16, 21, 33, 34, 39, 46, 53, 58, 61, 66, 67, 85, 86, 98	23, 27, 32, 37, 49, 50, 55, 62, 69, 74, 77, 82, 83, 101, 102, 114	Ground
73	AD02	78	94	Address/Data 02
74	AD05	75	91	Address/Data 05
75	AD00	80	96	Address/Data 00
76	AD03	79	95	Address/Data 03
77	SIORXD[0]			Southbridge Serial Receive
78	AD01	83	99	Address/Data 01
79	SIOTXD[0]			Southbridge Serial Transceive
80	/SW_PCI			?switch PCI?