Talk:Syscon SPI: Difference between revisions
Jump to navigation
Jump to search
(Dump notes on SPI bus sniffing) |
m (More notes) |
||
| Line 5: | Line 5: | ||
* The only substantial thing that differs between each of the beeps is the counters | * The only substantial thing that differs between each of the beeps is the counters | ||
> There is either noise on the line or the HW block responsible may be passing out uninitialized/don't care memory | > There is either noise on the line or the HW block responsible may be passing out uninitialized/don't care memory | ||
* No packets are transmitted from BE -> SC until the packet is kicked (0x8E100) | * There's some sort of scratchpad ram for the SPI registers in the CELL when sending packets to SC. No packets are transmitted from BE -> SC until the packet is kicked (0x8E100) | ||
* Seems to be some dedicated logic to deal with transmitting the buffer/registers via SPI | * Seems to be some dedicated logic to deal with transmitting the buffer/registers via SPI | ||
* SC always writes to 0x9104 after any SPI writes | * SC always writes to 0x9104 after any SPI writes | ||
* The Cell writes the full syscon header (0x10 bytes) to 0xA000 as part of the SPI transaction | |||
* Reading from the MMIO address space within the Cell doesn't trigger any SPI transactions | |||
* 0xb000 maps to 0x8D000 SB MMIO space | * 0xb000 maps to 0x8D000 SB MMIO space | ||
* 0xa000 maps to 0x8C000 SB MMIO space | * 0xa000 maps to 0x8C000 SB MMIO space | ||
* 0x9000 maps to 0x509000 SB MMIO space | * 0x9000 maps to 0x509000 SB MMIO space | ||
SB_INT Asserted before SC performs the initial read | SB_INT Asserted before SC performs the initial read | ||
Latest revision as of 04:03, 14 December 2021
Diff of Multiple triple-beep packets[edit source]
The following is a dump of 5 triple-beep packets to see if there are any major differences between them over the SPI bus.
- The only substantial thing that differs between each of the beeps is the counters
> There is either noise on the line or the HW block responsible may be passing out uninitialized/don't care memory
- There's some sort of scratchpad ram for the SPI registers in the CELL when sending packets to SC. No packets are transmitted from BE -> SC until the packet is kicked (0x8E100)
- Seems to be some dedicated logic to deal with transmitting the buffer/registers via SPI
- SC always writes to 0x9104 after any SPI writes
- The Cell writes the full syscon header (0x10 bytes) to 0xA000 as part of the SPI transaction
- Reading from the MMIO address space within the Cell doesn't trigger any SPI transactions
- 0xb000 maps to 0x8D000 SB MMIO space
- 0xa000 maps to 0x8C000 SB MMIO space
- 0x9000 maps to 0x509000 SB MMIO space
SB_INT Asserted before SC performs the initial read Read 0x9004 - SC -> BE | BE -> SC 1| 30 90 04 30 70 00 C6 | FF FF FC FF 00 00 01 2| 30 90 04 30 70 00 C6 | FF FF FC FF 00 00 01 3| 30 90 04 00 00 00 00 | F7 FF FC FF 00 00 01 4| 30 90 04 30 70 00 C6 | FF FF FC FF 00 00 01 5| 30 90 04 30 70 AB 6F | FF FF FC FF 00 00 01 SB_INT deasserted during once the last byte is transferred from the above read Read 0x9000 1| 30 90 00 18 70 00 86 | FF FF FC 00 00 00 0F 2| 30 90 00 18 70 00 86 | FF FF FC 00 00 00 0F 3| 30 90 00 18 70 00 86 | FF FF FC 00 00 00 0F 4| 30 90 00 18 70 00 86 | FF FF FC 00 00 00 0F 5| 30 90 00 18 70 00 86 | FF FF FC 00 00 00 0F Read 0xbff0 (BE Packet TX Counter) 1| 30 BF F0 FF FF FF FF | FF FF FE 00 F8 00 F8 2| 30 BF F0 FF FF FF FF | FF FF FE 00 F9 00 F9 3| 30 BF F0 FF FF FF FF | FF FF FA 00 FA 00 FA 4| 30 BF F0 FF FF FF FF | FF FF FE 00 FB 00 FB 5| 30 BF F0 FF FF FF FF | FF FF FE 00 FC 00 FC Read 0xaff4 (SC Packet RX Counter) 1| 30 AF F4 FF FF FF FF | FF FF FC 00 F7 00 F7 2| 30 AF F4 FF FF FF FF | FF FF FC 00 F8 00 F8 3| 30 AF F4 FF FF FF FF | FF FF FC 00 F9 00 F9 4| 30 AF F4 FF FF FF FF | FF FF FC 00 FA 00 FA 5| 30 AF F4 FF FF FF FF | FF FF FC 00 FB 00 FB Read 0xaff0 (SC Packet TX Counter) 1| 30 AF F0 FF FF FF FF | BF FF F7 00 FC 00 FC 2| 30 AF F0 FF FF FF FF | FF FF FF 00 FD 00 FD 3| 30 AF F0 FF FF FF FF | FF FF FF 00 FE 00 FE 4| 30 AF F0 FF FF FF FF | FF FF FF 00 FF 00 FF 5| 30 AF F0 FF FF FF FF | FF FF FF 01 00 01 00 Read 0xbff4 (BE Packet TX ACK Counter) 1| 30 BF F4 FF FF FF FF | FF FF FC 00 FC 00 FC 2| 30 BF F4 FF FF FF FF | FF FF FC 00 FD 00 FD 3| 30 BF F4 FF FF FF FF | FF FF FC 00 FE 00 FE 4| 30 BF F4 FF FF FF FF | FF FF FC 00 FF 00 FF 5| 30 BF F4 FF FF FF FF | FF FF FD 01 00 01 00 Read 0xb000 (0xd000 in MMIO space) 1| 30 B0 00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF | FF FF FE 16 01 16 20 00 00 80 4D 00 00 00 01 00 08 00 08 2| 30 B0 00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF | FF FF FE 16 01 16 20 00 00 80 4D 00 00 00 01 00 08 00 08 3| 30 B0 00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF | FF FF FE 16 01 16 20 00 00 80 4D 00 00 00 01 00 08 00 08 4| 30 B0 00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF | FF FF FE 16 01 16 20 00 00 80 4D 00 00 00 01 00 08 00 08 5| 30 B0 00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF | FF FF FE 16 01 16 20 00 00 80 4D 00 00 00 01 00 08 00 08 Read 0xb010 1| 30 B0 10 FF FF FF FF FF FF FF FF FF FF FF FF | FF FF FC 20 29 0A 00 00 00 01 B6 00 00 FD CB 2| 30 B0 10 FF FF FF FF FF FF FF FF FF FF FF FF | FF FF FC 20 29 0A 00 00 00 01 B6 00 00 FD CB 3| 30 B0 10 FF FF FF FF FF FF FF FF FF FF FF FF | FF FF FC 20 29 0A 00 00 00 01 B6 00 00 FD CB 4| 30 B0 10 FF FF FF FF FF FF FF FF FF FF FF FF | FF FF FC 20 29 0A 00 00 00 01 B6 00 00 FD CB 5| 30 B0 10 FF FF FF FF FF FF FF FF FF FF FF FF | FF FF FC 20 29 0A 00 00 00 01 B6 00 00 FD CB Write 0xaff4 (Syscon Packet RX counter) 1| 31 AF F4 00 F8 00 F8 | FF FF FF FF FF FF FF 2| 31 AF F4 00 F9 00 F9 | FF FF FF FF FF FF FF 3| 31 AF F4 00 FA 00 FA | 7F FF FF FF FF FF FB 4| 31 AF F4 00 FB 00 FB | BF FF F7 FF FF FF FF 5| 31 AF F4 00 FC 00 FC | FF FF FF FF FD FF FF Write 0x9104 (SC -> BE Doorbell? Maybe for the RX Counter written previously?) 1| 31 91 04 00 00 00 01 | FF FF FF FF FF FF FF 2| 31 91 04 00 00 00 01 | FF FF FF FF FF FF FF 3| 31 91 04 00 00 00 01 | FF FF FF FF FF FF FF 4| 31 91 04 00 00 00 01 | FF FF EF FF FF FF FF 5| 31 91 04 00 00 00 01 | F7 FF FF FF FF FF FF 1ms gap here... Read 0xbff0 1| 30 BF F0 FF FF FF FF | FF FF FC 00 F8 00 F8 2| 30 BF F0 FF FF FF FF | FF FF FC 00 F9 00 F9 3| 30 BF F0 FF FF FF FF | FF FF FC 00 FA 00 FA 4| 30 BF F0 FF FF FF FF | FF FF FC 00 FB 00 FB 5| 30 BF F0 FF FF FF FF | FF FF FC 00 FC 00 FC Read 0xaff4 1| 30 AF F4 FF FF FF FF | FF FF FC 00 F8 00 F8 2| 30 AF F4 FF FF FF FF | FF FF FC 00 F9 00 F9 3| 30 AF F4 FF FF FF FF | FF FF FC 00 FA 00 FA 4| 30 AF F4 FF FF FF FF | FF FF FC 00 FB 00 FB 5| 30 AF F4 FF FF FF FF | FF EF FC 00 FC 00 FC Read 0xaff0 1| 30 AF F0 FF FF FF FF | FF FF FF 00 FC 00 FC 2| 30 AF F0 FF FF FF FF | FF FF FF 00 FD 00 FD 3| 30 AF F0 FF FF FF FF | FF FF FF 00 FE 00 FE 4| 30 AF F0 FF FF FF FF | FF FF FF 00 FF 00 FF 5| 30 AF F0 FF FF FF FF | FF BF FF 01 00 01 00 Read 0xbff4 1| 30 BF F4 FF FF FF FF | FF FF FC 00 FC 00 FC 2| 30 BF F4 FF FF FF FF | 7F FF FC 00 FD 00 FD 3| 30 BF F4 FF FF FF FF | FF FF FC 00 FE 00 FE 4| 30 BF F4 FF FF FF FF | FF FF FC 00 FF 00 FF 5| 30 BF F4 FF FF FF FF | FF FF FD 01 00 01 00 Write 0xa000 1| 31 A0 00 16 01 16 20 00 00 80 4D 00 00 00 01 00 01 00 01 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 2| 31 A0 00 16 01 16 20 00 00 80 4D 00 00 00 01 00 01 00 01 | FF EF FF FF FF FF FF FF FF FF EF FF FF FF FF 7F FF FF FF 3| 31 A0 00 16 01 16 20 00 00 80 4D 00 00 00 01 00 01 00 01 | FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 4| 31 A0 00 16 01 16 20 00 00 80 4D 00 00 00 01 00 01 00 01 | F7 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 5| 31 A0 00 16 01 16 20 00 00 80 4D 00 00 00 01 00 01 00 01 | 7F FF FF FF FF FF FF FF FF FF FF DF FF FF FF FF FF FF FF Write 0xa010 1| 31 A0 10 00 00 00 00 | FF FF FF FF FF FF FF 2| 31 A0 10 00 00 00 00 | FF FF FF FF FF FF FF 3| 31 A0 10 00 00 00 00 | FF FF FF FF FF FF FF 4| 31 A0 10 00 00 00 00 | FF BF FF FF FF FF FF 5| 31 A0 10 00 00 00 00 | BF FF FF FF FF FF FF Write 0xa014 1| 31 A0 14 00 00 FE E3 | FF FF FF FF FF FF FF 2| 31 A0 14 00 00 FE E3 | FF FF FE FF FF FF FF 3| 31 A0 14 00 00 FE E3 | FF FF FF FF FF FF FF 4| 31 A0 14 00 00 FE E3 | FF FF FF FF FF FF FF 5| 31 A0 14 00 00 FE E3 | FF FF F7 FF FF FF FF Write 0xaff0 (SC Packet TX Counter) 1| 31 AF F0 00 FD 00 FD | FF BF FF FF FF FF FF 2| 31 AF F0 00 FE 00 FE | F7 FF FF FF FF FF FF 3| 31 AF F0 00 FF 00 FF | FF FF FF FF FF FF FF 4| 31 AF F0 01 00 01 00 | FF FF FF FF FF FF 7F 5| 31 AF F0 01 01 01 01 | FF FF FF FF FF FF FF Write 0x9104 (Doorbell?) 1| 31 91 04 00 00 00 01 | FF FF FF FF FF FF FF 2| 31 91 04 00 00 00 01 | F7 FF FF FF FF FF FF 3| 31 91 04 00 00 00 01 | 7F FF FF FF FF FF FF 4| 31 91 04 00 00 00 01 | FF FF FF BF FF FF FF 5| 31 91 04 00 00 00 01 | FF FF FF FF FF FF FF SB_INT asserted again at the end of the write of 0x9104 above Read 0x9004 1| 30 90 04 00 00 0F 00 | FF FF FC FF 00 00 01 2| 30 90 04 AB 6F 00 C6 | FF FF FC FF 00 00 01 3| 30 90 04 30 70 00 C6 | FF FF FC FF 00 00 01 4| 30 90 04 68 EE 3C 70 | FF FF FC FF 00 00 01 5| 30 90 04 30 70 00 C6 | FB FF FC FF 00 00 01 SB_INT deasserted after the 0x9004 read completes Read 0x9000 1| 30 90 00 18 70 00 86 | FF FD FC 00 00 00 0F 2| 30 90 00 18 70 00 86 | FF FF FC 00 00 00 0F 3| 30 90 00 18 70 00 86 | FF FF FC 00 00 00 0F 4| 30 90 00 18 70 00 86 | FF FF FC 00 00 00 0F 5| 30 90 00 18 70 00 86 | FF FF FC 00 00 00 0F 1ms gap here... Read 0xbff0 1| 30 BF F0 FF FF FF FF | FF FF FE 00 F8 00 F8 2| 30 BF F0 FF FF FF FF | FF FF FE 00 F9 00 F9 3| 30 BF F0 FF FF FF FF | FF FF FE 00 FA 00 FA 4| 30 BF F0 FF FF FF FF | FF FF FE 00 FB 00 FB 5| 30 BF F0 FF FF FF FF | FF FF FE 00 FC 00 FC Read 0xaff4 1| 30 AF F4 FF FF FF FF | FF FF FC 00 F8 00 F8 2| 30 AF F4 FF FF FF FF | BF FF F4 00 F9 00 F9 3| 30 AF F4 FF FF FF FF | FF FF FC 00 FA 00 FA 4| 30 AF F4 FF FF FF FF | FF FF F4 00 FB 00 FB 5| 30 AF F4 FF FF FF FF | FF FF FC 00 FC 00 FC Read 0xaff0 1| 30 AF F0 FF FF FF FF | FF FF FF 00 FD 00 FD 2| 30 AF F0 FF FF FF FF | FF FF FF 00 FE 00 FE 3| 30 AF F0 FF FF FF FF | FF BF FF 00 FF 00 FF 4| 30 AF F0 FF FF FF FF | BF FF F7 01 00 01 00 5| 30 AF F0 FF FF FF FF | FF FF FF 01 01 01 01 Read 0xbff4 1| 30 BF F4 FF FF FF FF | FF FF FC 00 FD 00 FD 2| 30 BF F4 FF FF FF FF | FF FF FC 00 FE 00 FE 3| 30 BF F4 FF FF FF FF | FF FF FC 00 FF 00 FF 4| 30 BF F4 FF FF FF FF | 7F FF FD 01 00 01 00 5| 30 BF F4 FF FF FF FF | FF FF FD 01 01 01 01