Talk:CELL BE: Difference between revisions

From PS3 Developer wiki
Jump to navigation Jump to search
No edit summary
Line 1: Line 1:
= Cell Broadband Engine =
= Cell Broadband Engine =
<div style="float:right">[[File:CellBE.jpg|200px|thumb|left|Cell Broadband Engine<br />CPU with heatplate<br />CXD2992AGB]]</div>
The Cell CPU has one 3.2Ghz PPE (Power Processor Element) with two threads and eight 3.2Ghz SPE (Synergistic Processing Elements).
The Cell CPU has one 3.2Ghz PPE (Power Processor Element) with two threads and eight 3.2Ghz SPE (Synergistic Processing Elements).


Revision as of 01:25, 3 June 2011

Cell Broadband Engine

Cell Broadband Engine
CPU with heatplate
CXD2992AGB

The Cell CPU has one 3.2Ghz PPE (Power Processor Element) with two threads and eight 3.2Ghz SPE (Synergistic Processing Elements).

The PPE is a general purpose CPU, while the eight SPE are geared towards processing data in parallel. One SPE is disabled to increase yield, so the PS3 can have at most 9 threads runnings at the same time (2 from PPE and 7 from SPE). Note that one SPE is reserved for the hypervisor, so PS3 programs can take advantage of 8 threads. Both the PPE and SPE of the Cell are 64 bit, and manipulate data in Big Endian.

Specifications

  • 1 PPE (Power Processor Element)
    • 3.2Ghz
    • 64 bit, Big Endian
    • 2 threads (can run at same time)
    • L1 cache: 32kB data + 32kB instruction
    • L2 cache: 512kB
    • Memory bus width: 64bit (serial)
    • VMX (Altivec) instruction set support
    • Full IEEE-754 compliant
  • 8 SPE (Synergistic Processing Element)
    • 3.2Ghz
    • 64 bit, Big Endian
    • 1 SPE disabled to improve chip yield (see: Unlocking the 8th SPE)
    • 1 SPE dedicated for hypervisor security
    • 256kB local store per SPE
    • 128 registers per SPE
    • Dual Issue (Each SPE can execute 2 instructions per clock)
    • IEEE-754 compliant in double precision (single precision round-towards-zero instead of round-towards-even)

There is a lot of info about CELL/BE on the Cell Programming IBM page.


Serial Numbers @ SKU

The Cell was introduced at 90nm. Later, PS3 model numbers starting with CECHG uses the 65nm version, while the PS3 Slim (CECH-20xx) used the 45nm version (See SKU Models and table below).

A sampling of the serial numbers by model number.

PS3 Model CELL Serial Die Tech Total Die Size Width x Length SPU size PPE Size
CECHA CXD2964GB 90nm 235.48mm² 19.17mm x 12.29mm 14.76mm² 28.86mm²
CECHB CXD2964GB 90nm 235.48mm² 19.17mm x 12.29mm 14.76mm² 28.86mm²
CECHC CXD2964GB 90nm 235.48mm² 19.17mm x 12.29mm 14.76mm² 28.86mm²
CECHD unreleased 90nm 235.48mm² 19.17mm x 12.29mm 14.76mm² 28.86mm²
CECHE CXD29?? 90nm 235.48mm² 19.17mm x 12.29mm 14.76mm² 28.86mm²
CECHF unreleased 90nm 235.48mm² 19.17mm x 12.29mm 14.76mm² 28.86mm²
CECHG CXD2981AGB 65nm 174.61mm² 15.59mm x 11.20mm 11.08mm² 19.60mm²
CECHH CXD2981GB 65nm 174.61mm² 15.59mm x 11.20mm 11.08mm² 19.60mm²
CECHI unreleased 65nm 174.61mm² 15.59mm x 11.20mm 11.08mm² 19.60mm²
CECHJ CXD2981GB 65nm 174.61mm² 15.59mm x 11.20mm 11.08mm² 19.60mm²
CECHK CXD2989AGB 65nm 174.61mm² 15.59mm x 11.20mm 11.08mm² 19.60mm²
CECHL CXD2990AGB 65nm 174.61mm² 15.59mm x 11.20mm 11.08mm² 19.60mm²
CECHM -? 65nm 174.61mm² 15.59mm x 11.20mm 11.08mm² 19.60mm²
CECHN unreleased 65nm 174.61mm² 15.59mm x 11.20mm 11.08mm² 19.60mm²
CECHO unreleased 65nm 174.61mm² 15.59mm x 11.20mm 11.08mm² 19.60mm²
CECHP -? 65nm 174.61mm² 15.59mm x 11.20mm 11.08mm² 19.60mm²
CECHQ CXD299? 65nm 174.61mm² 15.59mm x 11.20mm 11.08mm² 19.60mm²
CECH-20xx CXD2992AGB 45nm 115.46mm² 12.75mm x 9.06mm 6.47mm² 11.32mm²
CECH-21xx CXD2992AGB 45nm 115.46mm² 12.75mm x 9.06mm 6.47mm² 11.32mm²
CECH-25xx CXD2992GB 45nm 115.46mm² 12.75mm x 9.06mm 6.47mm² 11.32mm²
CECH-30xx -? 45nm? 115.46mm²? 12.75mm x 9.06mm? 6.47mm²? 11.32mm²?



Source: http://www.edepot.com/playstation3.html#PS3_CELL_CPU

Note: pad/pinouts are generally not available, please add them :)

Retrieved from "http://www.psdevwiki.com/ps3/index.php?title=Talk:CELL_BE&oldid=1993"