Talk:GbLAN: Difference between revisions

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(added sources for the mtu numbers)
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=== Marvell 88E6108-LAR1 (IC3503)===
=== Marvell 88E6108-LAR1 ===


<div style="float:right">[[File:Marvell 88E6108-LAR1.JPG|200px|thumb|left|144-TQFP<br />Marvell 88E6108-LAR1]]</div>
<div style="float:right">[[File:Marvell 88E6108-LAR1.JPG|200px|thumb|left|144-TQFP<br />Marvell 88E6108-LAR1]]</div>
Line 43: Line 43:
Port 7 (usable as TX/RX dif.pair): unused (tied to ground)</pre>
Port 7 (usable as TX/RX dif.pair): unused (tied to ground)</pre>


==== pinout ====  
==== Pinout IC3503====  
(prelimimairy, incomplete, WiP)
Productcode: 88E6108-B2-LAR1C000-P123 | PartNo.: 6-710-202-01
<div style="height:400px; overflow:auto">
<div style="height:400px; overflow:auto">
{| border="1" cellspacing="0" cellpadding="5" border="#999" class="wikitable" style="border:1px solid #999; border-collapse: collapse;"  
{| border="1" cellspacing="0" cellpadding="5" border="#999" class="wikitable" style="border:1px solid #999; border-collapse: collapse;"  
Line 52: Line 52:
| 1 || RST || rowspan="36" | Power / Led / Xtal etc || -
| 1 || RST || rowspan="36" | Power / Led / Xtal etc || -
|-
|-
| 2 || - || -
| 2 || AVDD || -
|-
|-
| 3 || - || -
| 3 || NC || No Connection
|-
|-
| 4 || - || -
| 4 || NC || No Connection
|-
|-
| 5 || - || -
| 5 || NC || No Connection
|-
|-
| 6 || - || -
| 6 || AVDD || -
|-
|-
| 7 || - || -
| 7 || XTAL_IN || -
|-
|-
| 8 || - || -
| 8 || XTAL_OUT || -
|-
|-
| 9 || - || -
| 9 || VDD_CORE || -
|-
|-
| 10 || - || -
| 10 || NC || No Connection
|-
|-
| 11 || - || -
| 11 || NC || No Connection
|-
|-
| 12 || - || -
| 12 || AVDD || -
|-
|-
| 13 || - || -
| 13 || NC || No Connection
|-
|-
| 14 || - || -
| 14 || NC || No Connection
|-
|-
| 15 || - || -
| 15 || P0_LED3 || -
|-
|-
| 16 || - || -
| 16 || P0_LED2 || -
|-
|-
| 17 || - || -
| 17 || VDD_CORE || -
|-
|-
| 18 || - || -
| 18 || P0_LED1 || -
|-
|-
| 19 || - || -
| 19 || P0_LED0 || -
|-
|-
| 20 || - || -
| 20 || VDDO_LED || -
|-
|-
| 21 || - || -
| 21 || P1_LED3 || -
|-
|-
| 22 || - || -
| 22 || VDD_CORE || -
|-
|-
| 23 || - || -
| 23 || P1_LED3 || -
|-
|-
| 24 || - || -
| 24 || P1_LED1 || -
|-
|-
| 25 || - || -
| 25 || P1_LED0 || -
|-
|-
| 26 || - || -
| 26 || VDDO_LED || -
|-
|-
| 27 || - || -
| 27 || P2_LED3 || -
|-
|-
| 28 || - || -
| 28 || P2_LED2 || -
|-
|-
| 29 || - || -
| 29 || P2_LED1 || -
|-
|-
| 30 || - || -
| 30 || P2_LED0 || -
|-
|-
| 31 || - || -
| 31 || VDD_CORE || -
|-
|-
| 32 || - || -
| 32 || MDC_PHY/PPU_EN || -
|-
|-
| 33 || - || -
| 33 || VDDO_SMI_PHY || -
|-
|-
| 34 || - || -
| 34 || MDIO_PHY || -
|-
|-
| 35 || - || -
| 35 || VDD_PLL || -
|-
|-
| 36 || - || -
| 36 || VDD_CORE || -
|-
|-
| 37 || P7_TXP || rowspan="5" | Port 7<br />(unused) || -
| 37 || P7_TXP || rowspan="5" | Port 7<br />(unused) || -
Line 172: Line 172:
| 61 || VDD_P3 || rowspan="46" | Port 3 (GMII) || -
| 61 || VDD_P3 || rowspan="46" | Port 3 (GMII) || -
|-
|-
| 62 || - || -
| 62 || P3_CLK125N || -
|-
|-
| 63 || - || -
| 63 || P3_TXEN/HALFDPX || -
|-
|-
| 64 || - || -
| 64 || P3_TXD7/MODE2 || -
|-
|-
| 65 || - || -
| 65 || P3_TXD6/MODE1 || -
|-
|-
| 66 || - || -
| 66 || VDD_CORE || -
|-
|-
| 67 || - || -
| 67 || P3_TXD5/MODE0 || -
|-
|-
| 68 || - || -
| 68 || P3_TXD4/ADDR4 || -
|-
|-
| 69 || - || -
| 69 || VDD0_P3 || -
|-
|-
| 70 || - || -
| 70 || P3_TXD3/ADDR3 || -
|-
|-
| 71 || - || -
| 71 || P3_TXD2/ADDR2 || -
|-
|-
| 72 || - || -
| 72 || P3_TXD1/ADDR1 || -
|-
|-
| 73 || - || -
| 73 || P3_TXD0/ADDR0 || -
|-
|-
| 74 || - || -
| 74 || P3_TXCLK || -
|-
|-
| 75 || - || -
| 75 || P3_GTXCLK || -
|-
|-
| 76 || - || -
| 76 || VDD0_P3 || -
|-
|-
| 77 || - || -
| 77 || P3_RXDV || -
|-
|-
| 78 || - || -
| 78 || VDD_CORE || -
|-
|-
| 79 || - || -
| 79 || P3_RXXEA || -
|-
|-
| 80 || - || -
| 80 || P3_RXD7 || -
|-
|-
| 81 || - || -
| 81 || P3_RXD6 || -
|-
|-
| 82 || - || -
| 82 || P3_RXD5 || -
|-
|-
| 83 || - || -
| 83 || P3_RXD4 || -
|-
|-
| 84 || - || -
| 84 || VDD_CORE || -
|-
|-
| 85 || - || -
| 85 || P3_RXD3 || -
|-
|-
| 86 || - || -
| 86 || VDDO_P3 || -
|-
|-
| 87 || - || -
| 87 || P3_RXD2 || -
|-
|-
| 88 || - || -
| 88 || P3_RXD1 || -
|-
|-
| 89 || - || -
| 89 || P3_RXD0 || -
|-
|-
| 90 || - || -
| 90 || P3_RXCLK || -
|-
|-
| 91 || VDD_CORE || -
| 91 || VDD_CORE || -
Line 238: Line 238:
| 94 || P3_ENABLE_PD || -
| 94 || P3_ENABLE_PD || -
|-
|-
| 95 || - || -
| 95 || INTn || -
|-
|-
| 96 || - || -
| 96 || MDIO_CPU || -
|-
|-
| 97 || - || -
| 97 || MDC_CPU || -
|-
|-
| 98 || - || -
| 98 || VDD_CORE || -
|-
|-
| 99 || - || -
| 99 || EE_DOUT || -
|-
|-
| 100 || - || -
| 100 || VDDO_SMI_CPU || -
|-
|-
| 101 || - || -
| 101 || EE_DIN/HD_FLOW_DIS || -
|-
|-
| 102 || - || -
| 102 || EE_CLK/FD_FLOW_DIS || -
|-
|-
| 103 || - || -
| 103 || EE_CS/EE_1K || -
|-
|-
| 104 || - || -
| 104 || VDD_CORE || -
|-
|-
| 105 || - || -
| 105 || SW_MODE0 PU || -
|-
|-
| 106 || - || -
| 106 || SW_MODE1 PU || -
|-
|-
| 107 || VSS ||  || Ground
| 107 || VSS ||  || Ground
Line 340: Line 340:
|}
|}
</div>
</div>
==== Pinout CN3501 ====
Connectortype: RJ45 modular jack with LED | PartNo.: 1-820-763-12
{| border="1" cellspacing="0" cellpadding="5" border="#999" class="wikitable" style="border:1px solid #999; border-collapse: collapse;"
|- bgcolor="#cccccc"
! Pin # !! Name !! Description
|-
| 1 || VCC || -
|-
| 2 || TP1+ || -
|-
| 3 || TP1- || -
|-
| 4 || TP2+ || -
|-
| 5 || TP2- || -
|-
| 6 || GND || -
|-
| 7 || TP3+ || -
|-
| 8 || TP3- || -
|-
| 9 || TP4+ || -
|-
| 10 || TP4- || -
|-
| 11 || VCC || -
|-
|}


=== Marvell Alaska 88E111R ===
=== Marvell Alaska 88E111R ===

Revision as of 03:10, 8 June 2011

Gigabit LAN

The PS3 has 1 Gigabit Ethernet port. The port accepts Auto-MDIX (automatic medium-dependent interface crossover), so no need for special crosscables when hooking up the PS3 direct to the PC.

Gigabit LAN chips used

A sample of the GbLAN chips in different PS3 models:

Type Size Speed Voltage Packaging Manufacturer Serial Number Description
- - - - 144-pin TQFP Marvell 88E6108-LAR1 Used in earlier models
- - - - 64-pin QFN Marvell Alaska 88E111R Used in Slim models


Marvell 88E6108-LAR1

144-TQFP
Marvell 88E6108-LAR1

Datasheet: (not available) 

productcode meaning:
88E6108-LAR1

Type: Ethernet
Speed : 1Gbps
Ports : 8
Package : 144-TQFP

(sorry, no explaination yet)

The Marvell 88E6108-LAR1 is sort of a switching hub chip, with several ports that can be used in different configurations: 

Port 0 (usuable as MDI 4 dif.pair) : unused (tied to ground)
Port 1 (usuable as MDI 4 dif.pair) : unused (tied to ground)
Port 2 (usuable as MDI 4 dif.pair) : wired to external UTP connector
Port 3 (GMII): Wired to SB
Port 4 (usable as TX/RX dif.pair)(100FX): wired to Wifi
Port 5 (usable as TX/RX dif.pair): unused (tied to ground)
Port 6 (usable as TX/RX dif.pair): unused (tied to ground)
Port 7 (usable as TX/RX dif.pair): unused (tied to ground)

Pinout IC3503

Productcode: 88E6108-B2-LAR1C000-P123 | PartNo.: 6-710-202-01

Pin # Name Port Description
1 RST Power / Led / Xtal etc -
2 AVDD -
3 NC No Connection
4 NC No Connection
5 NC No Connection
6 AVDD -
7 XTAL_IN -
8 XTAL_OUT -
9 VDD_CORE -
10 NC No Connection
11 NC No Connection
12 AVDD -
13 NC No Connection
14 NC No Connection
15 P0_LED3 -
16 P0_LED2 -
17 VDD_CORE -
18 P0_LED1 -
19 P0_LED0 -
20 VDDO_LED -
21 P1_LED3 -
22 VDD_CORE -
23 P1_LED3 -
24 P1_LED1 -
25 P1_LED0 -
26 VDDO_LED -
27 P2_LED3 -
28 P2_LED2 -
29 P2_LED1 -
30 P2_LED0 -
31 VDD_CORE -
32 MDC_PHY/PPU_EN -
33 VDDO_SMI_PHY -
34 MDIO_PHY -
35 VDD_PLL -
36 VDD_CORE -
37 P7_TXP Port 7
(unused)		 -
38 P7_TXN -
39 P7_VDDAH Ground
40 P7_RXP -
41 P7_RXN -
42 VSS Ground
43 P6_RXP Port 6
(unused)		 -
44 P6_RXN -
45 P6_VDDAH Ground
46 P6_TXN -
47 P6_TXP -
48 VDD_CORE -
49 P5_TXP Port 5
(unused)		 -
50 P5_TXN -
51 P5_VDDAH Ground
52 P5_RXP -
53 P5_RXN -
54 VSS Ground
55 P4_RXN Port 4 (100FX) -
56 P4_RXP -
57 P4_VDDAH -
58 P4_TXN -
59 P4_TXP -
60 VDD_CORE -
61 VDD_P3 Port 3 (GMII) -
62 P3_CLK125N -
63 P3_TXEN/HALFDPX -
64 P3_TXD7/MODE2 -
65 P3_TXD6/MODE1 -
66 VDD_CORE -
67 P3_TXD5/MODE0 -
68 P3_TXD4/ADDR4 -
69 VDD0_P3 -
70 P3_TXD3/ADDR3 -
71 P3_TXD2/ADDR2 -
72 P3_TXD1/ADDR1 -
73 P3_TXD0/ADDR0 -
74 P3_TXCLK -
75 P3_GTXCLK -
76 VDD0_P3 -
77 P3_RXDV -
78 VDD_CORE -
79 P3_RXXEA -
80 P3_RXD7 -
81 P3_RXD6 -
82 P3_RXD5 -
83 P3_RXD4 -
84 VDD_CORE -
85 P3_RXD3 -
86 VDDO_P3 -
87 P3_RXD2 -
88 P3_RXD1 -
89 P3_RXD0 -
90 P3_RXCLK -
91 VDD_CORE -
92 P3_CRS -
93 P3_COL -
94 P3_ENABLE_PD -
95 INTn -
96 MDIO_CPU -
97 MDC_CPU -
98 VDD_CORE -
99 EE_DOUT -
100 VDDO_SMI_CPU -
101 EE_DIN/HD_FLOW_DIS -
102 EE_CLK/FD_FLOW_DIS -
103 EE_CS/EE_1K -
104 VDD_CORE -
105 SW_MODE0 PU -
106 SW_MODE1 PU -
107 VSS Ground
108 RESETn -
109 VSS Port 2 (MDI) Ground
110 P2_MDIN3 -
111 P2_MDIP3 -
112 P2_AVDD -
113 P2_MDIN2 -
114 P2_MDIP2 -
115 P2_MDIN1 -
116 P2_MDIP1 -
117 P2_AVDD -
118 P2_AVDD -
119 P2_MDIN0 -
120 P2_MDIP0 -
121 VSS Port 1 (MDI) Ground
122 P1_MDIN3 -
123 P1_MDIP3 -
124 P1_AVDD -
125 P1_MDIN2 -
126 P1_MDIP2 -
127 P1_MDIN1 -
128 P1_MDIP1 -
129 P1_AVDD -
130 P1_AVDD -
131 P1_MDIN0 -
132 P1_MDIP0 -
133 VSS Port 0 (MDI) Ground
134 P0_MDIN3 -
135 P0_MDIP3 -
136 P0_AVDD -
137 P0_MDIN2 -
138 P0_MDIP2 -
139 P0_MDIN1 -
140 P0_MDIP1 -
141 P0_AVDD -
142 P0_AVDD -
143 P0_MDIN0 -
144 P1_MDIP0 -


Pinout CN3501

Connectortype: RJ45 modular jack with LED | PartNo.: 1-820-763-12

Pin # Name Description
1 VCC -
2 TP1+ -
3 TP1- -
4 TP2+ -
5 TP2- -
6 GND -
7 TP3+ -
8 TP3- -
9 TP4+ -
10 TP4- -
11 VCC -

Marvell Alaska 88E111R

Productsheet 

productcode meaning:
88E111R

Type: Ethernet
Speed : 1Gbps
Package : 64-pin QFN

(sorry, no explaination yet)


pinout

(nothing here, please help fill this in)

Pin # Name Port Description
1 - -
2 - -
3 - -
4 - -
5 - -
6 - -
7 - -
8 - -
9 - -
10 - -
11 - -
12 - -
13 - -
14 - -
15 - -
16 - -
17 - -
18 - -
19 - -
20 - -
21 - -
22 - -
23 - -
24 - -
25 - -
26 - -
27 - -
28 - -
29 - -
30 - -
31 - -
32 - -
33 - -
34 - -
35 - -
36 - -
37 - -
38 - -
39 - -
40 - -
41 - -
42 - -
43 - -
44 - -
45 - -
46 - -
47 - -
48 - -
49 - -
50 - -
51 - -
52 - -
53 - -
54 - -
55 - -
56 - -
57 - -
58 - -
59 - -
60 - -
61 - -
62 - -
63 - -
64 - -

Jumbo frames

From Linux perspective (under OtherOS <=3.15), the old drivers set the MTU to 2308, while newer versions set the MTU of 1518. This could be a hypervisor restriction (needs research).

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