Talk:Unlocking the 8th SPE: Difference between revisions
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(Created page with "From CELL BE Configuration Docs, We can identify faulty SPE's over SPI bus it seems. You could also unlock these via SPI bus during configuration ring. ~~~~ <pre> Read Partial Go...") |
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From CELL BE Configuration Docs, We can identify faulty SPE's over SPI bus it seems. You could also unlock these via SPI bus during configuration ring. [[User: | From CELL BE Configuration Docs, We can identify faulty SPE's over SPI bus it seems. You could also unlock these via SPI bus during configuration ring. [[User:Defyboy|Admin]] 06:25, 1 May 2011 (CDT) | ||
<pre> | <pre> | ||
Read Partial Good Register (rd_partial_good) | Read Partial Good Register (rd_partial_good) | ||
Latest revision as of 04:43, 6 April 2023
From CELL BE Configuration Docs, We can identify faulty SPE's over SPI bus it seems. You could also unlock these via SPI bus during configuration ring. Admin 06:25, 1 May 2011 (CDT)
Read Partial Good Register (rd_partial_good) The rd_partial_good register indicates which SPEs are good. During Cell BE-processor manufacturing tests, manufacturing identifies faulty SPEs on the chip. When a bad SPE is detected, manufacturing programs fuse bits on the Cell BE processor to identify the faulty SPEs. A ‘0’ in the rd_partial_good register implies that the SPE is good. A ‘1’ indicates that the SPE is faulty. Any SPEs marked as faulty in this register are disabled internally. Specifying the corresponding SPE as enabled in the configuration ring does not overwrite the effects of the fuse settings contained in this register. Because the spe_available MMIO register receives its value from the SPE Disable field on the configuration ring during POR, the external system controller must read the rd_partial_good register before the configuration ring write has taken place in order to set the SPE Disable field to match the rd_partial_good register.