Talk:RAM: Difference between revisions
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: without actual tweet hard to discuss... It is in the nature of /XDR/ RAM to be Random Accessable Memory in the first place ;) As long as you stick to that one module at a time. There is no HV/W^X etc on that hardware level (which takes place in the CPU / OS instead) [[User:Euss|Euss]] ([[User talk:Euss|talk]]) 12:13, 27 August 2014 (EDT) | : without actual tweet hard to discuss... It is in the nature of /XDR/ RAM to be Random Accessable Memory in the first place ;) As long as you stick to that one module at a time. There is no HV/W^X etc on that hardware level (which takes place in the CPU / OS instead) [[User:Euss|Euss]] ([[User talk:Euss|talk]]) 12:13, 27 August 2014 (EDT) | ||
:: sorry about that, should've taken a picture :P i'm not as fast as you when you're awake :) 17:36, 27 August 2014 [[User:Zecoxao]] | :: sorry about that, should've taken a picture :P i'm not as fast as you when you're awake :) 17:36, 27 August 2014 [[User:Zecoxao]] | ||
::: According to wikipedia: each chip has a low-speed serial bus used to determine its capabilities and configure its interface. This consists of three shared inputs: a reset line (RST), a serial command input (CMD) and a serial clock (SCK), and serial data in/out lines (SDI and SDO) that are daisy-chained together and eventually connect to a single pin on the memory controller. [http://en.wikipedia.org/wiki/XDR_DRAM#Protocol Source] 19:25, 27 August 2014 [[User:NiceShot]] | |||
Latest revision as of 21:17, 27 August 2014
source: http://www.edepot.com/playstation3.html#PS3_Motherboard
Direct Rambus Technology[edit source]
A PDF from Stanford explains this very well.
K4Y50164UE-JCB3 Datasheet[edit source]
A very helpful PDF explaining everything there is to know about this chip.
http://www.keepandshare.com/doc/4521123/k4y50044ue-pdf-3-5-meg?da=y
Backdoor?[edit source]
According to a tweet by (already deleted, source), there is a backdoor in XDR Ram that allows the attacker to write to any place in the memory. 16:40, 27 August 2014 User:Zecoxao
- without actual tweet hard to discuss... It is in the nature of /XDR/ RAM to be Random Accessable Memory in the first place ;) As long as you stick to that one module at a time. There is no HV/W^X etc on that hardware level (which takes place in the CPU / OS instead) Euss (talk) 12:13, 27 August 2014 (EDT)
- sorry about that, should've taken a picture :P i'm not as fast as you when you're awake :) 17:36, 27 August 2014 User:Zecoxao
- According to wikipedia: each chip has a low-speed serial bus used to determine its capabilities and configure its interface. This consists of three shared inputs: a reset line (RST), a serial command input (CMD) and a serial clock (SCK), and serial data in/out lines (SDI and SDO) that are daisy-chained together and eventually connect to a single pin on the memory controller. Source 19:25, 27 August 2014 User:NiceShot
- sorry about that, should've taken a picture :P i'm not as fast as you when you're awake :) 17:36, 27 August 2014 User:Zecoxao