Talk:RAM: Difference between revisions

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== Main System Memory ==
source: http://www.edepot.com/playstation3.html#PS3_Motherboard
 
The PS3 has 256MB of 64 bit bus Rambus XDR main system memory. Some models use four 64MB Samsung chips, while other models uses four 64MB Elpida chips.
 
A sample of the Memory chips in different PS3 models:
{| border="1" cellspacing="0" cellpadding="5" border="#999" class="wikitable" style="border:1px solid #999; border-collapse: collapse;"
|- bgcolor="#cccccc"
! Type !! Size !! Speed !! Voltage !! Packaging !! Manufacturer !! Serial Number !! Description
|-
| Rambus XDR || 64MB || 400MHz || 1.8V+/-0.09V || FBGA-104 || Elpida || EDX5116ACSE-3C-E || 256MB total (4 chips) for PS3 System Memory (Initial Models)
|-
| Rambus XDR || 64MB || 400MHz || 1.8V+/-0.09V || FBGA-104 || Samsung || K4Y50164UC-JCB3 || 256MB total (4 chips) for PS3 System Memory (Initial Models)
|-
| Rambus XDR || 64MB || 400MHz || 1.8V+/-0.09V || FBGA-100 || Samsung || K4Y50164UE-JCB3 || 256MB total (4 chips) for PS3 System Memory (CECHG,CECHK)
|-
| Rambus XDR || 64MB || 400MHz || 1.8V+/-0.09V || FBGA-104 || Elpida || X5116ADSE-3C-E || 256MB total (4 chips) for PS3 System Memory (CECH-20xx)
|-
| Rambus XDR || 128MB || 400MHz || 1.5V+/-0.075V || FBGA-150 || Elpida || X1032BASE-3C-F || 256MB total (2 chips) for PS3 System Memory (CECH-21xx and later)
|-
|}
:
 
=== Elpida EDX5116ACSE-3C-E ===
 
<div style="float:right">[[File:EDX5116ACSE-3C-E.png|200px|thumb|left|104-ball FBGA<br />Elpida EDX5116ACSE-3C-E]]</div>
 
Datasheet: [http://www.elpida-korea.com/pdfs/E0881E20.pdf Elpida EDX5116ACSE]
 
<pre>productcode meaning:
E - Elpida Memory
D - Type : Monolithic Device
X - Product Family : XDR RAM
51 - Density : 512M (x16bit)
16 - Organisation : x16bit
A - Supply Voltage : 1.8V, DRSL
C - Die Revision: C
SE - Package : FBGA (with back cover)
-
3C - Speed : 3.2G (tRAC = 35, C Bin)
-
E - Environmental Code : Lead Free</pre>
 
 
=== Samsung K4Y50164UC-JCB3 ===
 
<div style="float:right">[[File:K4Y50164UC-JCB3.png|200px|thumb|left|100-ball FBGA<br />Samsung K4Y50164UC-JCB3]]</div>
 
Datasheet: [http://www.samsung.com/global/system/business/semiconductor/product/2007/6/11/XDR_RDRAM/XDRDRAM/Component/512Mbit/K4Y50164UC/ds_k4y50xx4uc_rev11.pdf Samsung K4Y50164UC-JCB3]
 
<pre>productcode meaning:
K - Samsung Memory
4 - DRAM
Y - Product : XDR RAM
50 - Density : 512M, 32K/16ms(0,49us)
16 - Organisation : x16
4 - Banks : 8
U - Interface : DRSL(1.8V, 1.2V)
C - Generation : 4th
-
J - Packagetype: BOC lead free
C - Temperature & Power: Commercial, Normal Power
B3 - Speed (Data frequency, tRAC, tRC) : 3.2Gbps, 35ns, 24cycles</pre>
 
 
=== Samsung K4Y50164UE-JCB3 ===
 
<div style="float:right">[[File:K4Y50164UE-JCB3.png|200px|thumb|left|104-ball FBGA<br />Samsung K4Y50164UE-JCB3]]</div>
 
Datasheet: [http://www.samsung.com/global/system/business/semiconductor/product/2007/6/11/XDR_RDRAM/XDRDRAM/Component/512Mbit/K4Y50164UE/ds_k4y50xx4ue_rev10.pdf Samsung K4Y50164UE-JCB3]


<pre>productcode meaning:
== Direct Rambus Technology ==
K - Samsung Memory
4 - DRAM
Y - Product : XDR RAM
50 - Density : 512M, 32K/16ms(0,49us)
16 - Organisation : x16
4 - Banks : 8
U - Interface : DRSL(1.8V, 1.2V)
E - Generation : 6th
-
J - Packagetype: BOC lead free
C - Temperature & Power: Commercial, Normal Power
B3 - Speed (Data frequency, tRAC, tRC) : 3.2Gbps, 35ns, 24cycles</pre>


A PDF from Stanford explains this very well.


=== Elpida X5116ADSE-3C-E ===
[http://www.stanford.edu/class/ee382/MISC/rambus.pdf Direct Rambus Technology]


<div style="float:right">[[File:X5116ADSE-3C-E.png|200px|thumb|left|104-ball FBGA<br />Elpida X5116ADSE-3C-E]]</div>
== K4Y50164UE-JCB3 Datasheet ==


Datasheet: [http://www.elpida.com/eolpdfs/E1033E40_EOL.pdf Elpida X5116ADSE-3C-E]
A very helpful PDF explaining everything there is to know about this chip.


<pre>productcode meaning:
http://www.keepandshare.com/doc/4521123/k4y50044ue-pdf-3-5-meg?da=y
X - Product Family : XDR RAM
51 - Density : 512M (x16bit)
16 - Organisation : x16bit
A - Supply Voltage : 1.8V, DRSL
D - Die Revision: D
SE - Package : FBGA (with back cover)
-
3C - Speed : 3.2G (tRAC = 35, C Bin)
-
E - Environmental Code : Lead Free</pre>
 
 
=== Elpida X1032BASE-3C-F ===
 
Datasheet: E1332E50 (EOL)
 
<pre>productcode meaning:
E - Elpida Memory
D - Type : Monolithic Device
X - Product Family : XDR RAM
13 - Density : 1Gbit (128MB) 32Mbitx32
32 - Organisation : x32bit
B - Supply Voltage : 1.5V +/- 0.075V, DRSL
A - Die Revision: A
SE - Package : FBGA (with back cover)
-
3C - Speed : 3.2G (tRAC = 35, C Bin)
-
F - Environmental Code : Lead & Halogen Free</pre>
 
== Graphics Memory ==
256MB of GDDR3 memory is located inside the RSX chip using four 64MB Samsung chips.
 
{| border="1" cellspacing="0" cellpadding="5" border="#999" class="wikitable" style="border:1px solid #999; border-collapse: collapse;"
|- bgcolor="#cccccc"
! Type !! Size !! Speed !! Voltage !! Packaging !! Manufacturer !! Serial Number !! Description
|-
| GDDR3 || 64MB || 700MHz ||  ||  || Samsung || K4J52324QC-SC14 || 256MB total (4 chips) for PS3 Graphics Memory
|-
|}
:
 
== PS2 Compatibility Memory ==
The earlier models with hardware PS2 compatibility also contained an extra 32MB of RDRAM using two 16MB Samsung chips.
 
{| border="1" cellspacing="0" cellpadding="5" border="#999" class="wikitable" style="border:1px solid #999; border-collapse: collapse;"
|- bgcolor="#cccccc"
! Type !! Size !! Speed !! Voltage !! Packaging !! Manufacturer !! Serial Number !! Description
|-
| RDRAM || 16MB || 800MHz ||  || 54-pin || Samsung || K4R271669F || 32MB total (2 chips) for Hardware PS2 Compatibility System Memory
|-
|}
:
 
source: http://www.edepot.com/playstation3.html#PS3_Motherboard


todo: add datasheet links, more package & pad/pin info, cleanup
== Backdoor? ==
According to a tweet by (already deleted, [https://twitter.com/RichDevX/status/504389462496137217 source]), there is a backdoor in XDR Ram that allows the attacker to write to any place in the memory. 16:40, 27 August 2014‎ [[User:Zecoxao]]
: without actual tweet hard to discuss... It is in the nature of /XDR/ RAM to be Random Accessable Memory in the first place ;) As long as you stick to that one module at a time. There is no HV/W^X etc on that hardware level (which takes place in the CPU / OS instead) [[User:Euss|Euss]] ([[User talk:Euss|talk]]) 12:13, 27 August 2014 (EDT)
:: sorry about that, should've taken a picture :P i'm not as fast as you when you're awake :) 17:36, 27 August 2014 [[User:Zecoxao]]
::: According to wikipedia: each chip has a low-speed serial bus used to determine its capabilities and configure its interface. This consists of three shared inputs: a reset line (RST), a serial command input (CMD) and a serial clock (SCK), and serial data in/out lines (SDI and SDO) that are daisy-chained together and eventually connect to a single pin on the memory controller. [http://en.wikipedia.org/wiki/XDR_DRAM#Protocol Source] 19:25, 27 August 2014 [[User:NiceShot]]

Latest revision as of 21:17, 27 August 2014

source: http://www.edepot.com/playstation3.html#PS3_Motherboard

Direct Rambus Technology[edit source]

A PDF from Stanford explains this very well.

Direct Rambus Technology

K4Y50164UE-JCB3 Datasheet[edit source]

A very helpful PDF explaining everything there is to know about this chip.

http://www.keepandshare.com/doc/4521123/k4y50044ue-pdf-3-5-meg?da=y

Backdoor?[edit source]

According to a tweet by (already deleted, source), there is a backdoor in XDR Ram that allows the attacker to write to any place in the memory. 16:40, 27 August 2014‎ User:Zecoxao

without actual tweet hard to discuss... It is in the nature of /XDR/ RAM to be Random Accessable Memory in the first place ;) As long as you stick to that one module at a time. There is no HV/W^X etc on that hardware level (which takes place in the CPU / OS instead) Euss (talk) 12:13, 27 August 2014 (EDT)
sorry about that, should've taken a picture :P i'm not as fast as you when you're awake :) 17:36, 27 August 2014 User:Zecoxao
According to wikipedia: each chip has a low-speed serial bus used to determine its capabilities and configure its interface. This consists of three shared inputs: a reset line (RST), a serial command input (CMD) and a serial clock (SCK), and serial data in/out lines (SDI and SDO) that are daisy-chained together and eventually connect to a single pin on the memory controller. Source 19:25, 27 August 2014 User:NiceShot
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