Editing User talk:Kozarovv

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===ps2_netemu emitter===
== PS2 netemu ==
I need to clean this up little bit before posting on ps2 emu page. This is opd list of recompiler functions that are responsible for emitting ppc translated opcodes.
===Picard notes - edited===
 
<pre>
<pre>
0x73C358 ppc_emitter_clrlwi
---------------------------------------------------------------------------------------------------------------------------------------
0x73C370 ppc_emitter_add
0x00: end, branch if is_cnf == 0(false), ret *sub_46BD4, else do WE HAVE A CONFIG: cd setup
0x73C388 ppc_emitter_mulhw
0x01: value2, value3(max 59): exec start_iso_148EF0(value2, *entrie), *entrie from *vtab_9363F8 by index(value3)
0x73C3A0 ppc_emitter_mulhdu
 
0x73C3B8 ppc_emitter_mulhd
 
0x73C3D0 ppc_emitter_mtvscr
0x02: config_cmd_0x02(value2); store value2 on (u32)*0xB530DC
0x73C3E8 ppc_emitter_mtocrf
0x03: config_cmd_0x03(void); set (u8)*0x94A290 to 0 (default 1)
0x73C400 ppc_emitter_mtlr
0x04: config_cmd_0x04(u32 value2); todo...
0x73C418 ppc_emitter_mtctr
 
0x73C430 ppc_emitter_mtcrf
0x06: config_cmd_0x06(void); set (u32)*0x40181B20, (u32)*0x40181B24, (u32)*0x40181B28 and (u32)*0x40181B2C to 0x14F80
0x73C448 ppc_emitter_mfvscr
0x07: config_cmd_0x07(value2); store (u32)value2 on *0x94A27C (default 1)
0x73C460 ppc_emitter_mftb
-----------------------------------------------------------------------------------
0x73C478 ppc_emitter_mfocrf
0x08: config_cmd_0x08(u64 arg[4]); = Clamping a-like. VU 0/1 Patch by mask pattern
0x73C490 ppc_emitter_mflr
      arg[0] = ((value2 <<32) | value3)
0x73C4A8 ppc_emitter_mfctr
      arg[1] = ((value4 <<32) | value5)
0x73C4C0 ppc_emitter_mfcr
      arg[2] = ((value6 <<32) | value7)
0x73C4D8 ppc_emitter_lwzx
      arg[3] = ((value8 <<32) | value9)
0x73C4F0 ppc_emitter_lwzu
-----------------------------------------------------------------------------------
0x73C508 ppc_emitter_lwz
0x09: value2(count) = DOUBLE UINT32_t_EE_MEMPATCH
0x73C520 ppc_emitter_lwsync
     
0x73C538 ppc_emitter_lwbrx
      struct data {    // size 0x18
0x73C550 ppc_emitter_lvxl
        u32 unk_00;    // 0x00: value3
0x73C568 ppc_emitter_lvx
        u32 unk_04;    // 0x04: padding
0x73C580 ppc_emitter_lvsr
        u64 unk_08;    // 0x08: ((value4 <<32) | value5)
0x73C598 ppc_emitter_lvsl
        u64 unk_10;    // 0x10: ((value6 <<32) | value7)
0x73C5B0 ppc_emitter_lvlx
      }
0x73C5C8 ppc_emitter_lvewx
     
0x73C5E0 ppc_emitter_lvehx
      sub_122904(1, 1, data); for count
0x73C5F8 ppc_emitter_lvebx
-----------------------------------------------------------------------------------
0x73C610 ppc_emitter_lhzx
0x0A: value2 = count = UINT32_t_EE_MEMPATCH
0x73C628 ppc_emitter_lhzu
      struct data {    // size 0x18
0x73C640 ppc_emitter_lhz
        u32 unk_00;    // 0x00: value3
0x73C658 ppc_emitter_lhbrx
        u32 unk_04;    // 0x04: padding
0x73C670 ppc_emitter_lfsx
        u64 unk_08;    // 0x08: (u32)value4
0x73C688 ppc_emitter_lfs
        u64 unk_10;    // 0x10: (u32)value5
0x73C6A0 ppc_emitter_lfdx
      }
0x73C6B8 ppc_emitter_lfd
     
0x73C6D0 ppc_emitter_ldx
      sub_122904(2, 4, &var_198); in loop, to config end
0x73C6E8 ppc_emitter_ldbrx
-----------------------------------------------------------------------------------
0x73C700 ppc_emitter_ld
0x0B: MECHA_config_cmd_0x0B(*thr_mecha_obj, value2); try again if not ret 0    todo... = GAMEDISC_PATCH (-0xC per offset) jump table at 0x131FA0 seems to be disc type selector (DVD, DVD9, CD, CD MODE1, CDDA)
0x73C718 ppc_emitter_lbzx
-----------------------------------------------------------------------------------
0x73C730 ppc_emitter_lbzu
0x0C: X = (value2 >>16) 0, 1 or 2; Y = (value2 & 0xFFFF)
0x73C748 ppc_emitter_lbz
      MECHA_config_cmd_0x0C_0(*thr_mecha_obj, Y), set (u32)thr_mecha_obj.unk_004C to Y and set (u32)thr_mecha_obj.unk_005C to Y /// bytes? Always multiply of 8.  
0x73C760 ppc_emitter_isync
      MECHA_config_cmd_0x0C_1(*thr_mecha_obj, X), set (u32)thr_mecha_obj.unk_0048 to X
0x73C778 ppc_emitter_fsubs
-----------------------------------------------------------------------------------
0x73C790 ppc_emitter_fsub
0x0D: store (u8)value2(0 or 1) on *0xB4A310
0x73C7A8 ppc_emitter_fsqrts
0x0E: config_cmd_0x0E(value2)
0x73C7C0 ppc_emitter_fsqrt
0x0F: config_cmd_0x0F(u32 value2, u32 value3) = add/sub accu
0x73C7D8 ppc_emitter_fsel
0x10: config_cmd_0x10(u32 value2, u32 value3) = accu
0x73C7F0 ppc_emitter_frsqrte
0x11:
0x73C808 ppc_emitter_frsp
0x12: value2 = count of next (u32)values, do config_cmd_0x12(value) for each = Registers values patch?
0x73C820 ppc_emitter_fres
0x13: config_cmd_0x13set(), set *0x1BDC790 to ((value2 <<32) | value3) Memory card related (timing? reported free space?), Value 2 seems to be always 0
0x73C838 ppc_emitter_fnmsubs
0x14: sub_139354(), store 1 on 0x247E9E8, also done in thr_SYS() if if stat_flag[45:45] is set
0x73C850 ppc_emitter_fsub__
0x15: config_cmd_0x15(u32 value2(0 or 1)), check 256 u32 from 0x4003A2C0, if (value & 0xFF800000) == 0x30000000, replace with 0x35003F80 // Old good andi to ori fix.. moar: https://web.archive.org/web/20041211174320/http://nachbrenner.pcsx2.net:80/chapter3.html (in tut is a mistake 34)
0x73C868 ppc_emitter_fnmadds
 
0x73C880 ppc_emitter_fnmadd
0x17: store (u8)value2 on *0x2A0DC52
0x73C898 ppc_emitter_fneg
 
0x73C8B0 ppc_emitter_fnabs
0x19: pad_set_0xB5C500(), store 1 on 0xB5C500
0x73C8C8 ppc_emitter_fmuls
0x1A: set 0x40300350 to 1
0x73C8E0 ppc_emitter_fmul
0x1B: set 0x40300360 to 1
0x73C8F8 ppc_emitter_fmsubs
0x1C: store (u8)value2 on *0x949FD5
0x73C910 ppc_emitter_fmsub
0x1D: store (u8)value2 on *0xB5B87A
0x73C928 ppc_emitter_fmr
0x1E: store (u8)value2 on *0xB5C501
0x73C940 ppc_emitter_fmadds
0x1F: set_sub_121FE4(value2), store (u32)value2 on *0xB56B80
0x73C958 ppc_emitter_fmadd
0x20: store (u64)((value2 <<32) | value3) on *0x949FC8
0x73C970 ppc_emitter_fdivs
-----------------------------------------------------------------------------------
0x73C988 ppc_emitter_fdiv
0x21: value2: 0: set (u8)*0x94A291 to 0 and (u8)*0x2A0DC5C to 0
0x73C9A0 ppc_emitter_fctiwz
              1: set (u8)*0x94A291 to 0 and (u8)*0x2A0DC5C to 1
0x73C9B8 ppc_emitter_fctiw
              2: set (u8)*0x94A291 to 1 and (u8)*0x2A0DC5C to 0
0x73C9D0 ppc_emitter_fctidz
-----------------------------------------------------------------------------------
0x73C9E8 ppc_emitter_fctid
0x22: set (u8)thr_mecha_obj.unk_00EA to 1
0x73CA00 ppc_emitter_fcmpu
0x23: sub_123080(), copy 256 byte from 0x40181A10 to 0x40182110 and set 0x40182120, 0x40181B24, 0x40181B28 and 0x40181B2C to 0x14E00
0x73CA18 ppc_emitter_fcmpo
0x24: config_cmd_0x24(), store ((value2 <<32) | value3) on *0xB5C1B8
0x73CA30 ppc_emitter_fcfid
 
0x73CA48 ppc_emitter_fadds
0x26: config_cmd_0x26(u32 value2, u32 value3); add accu
0x73CA60 ppc_emitter_fadd
0x27: config_cmd_0x27(u32 value2, u32 value3); accu
0x73CA78 ppc_emitter_fabs
0x28: MECHA_config_cmd_0x28(*thr_mecha_obj, u32 value2); set thr_mecha_obj.unk_0050, value2 <4
0x73CA90 ppc_emitter_extsw
0x29: MECHA_config_cmd_0x29(*thr_mecha_obj, value2, value3); set (u32)thr_mecha_obj.unk_0054 to value2 and (u32)thr_mecha_obj.unk_0058 to value3 (default val2 = 1f40{8000} val3 = bb80{48000})
0x73CAA8 ppc_emitter_extsh
0x2A: set (u8)*0xB52BBD to 1 (used only in one game, without it menu is not showing, but game still work. On pcsx2 situation is opposite, menu is ok, but there is no backgroud)
0x73CAC0 ppc_emitter_extsb
0x2B: MECHA_config_cmd_0x2B(*thr_mecha_obj, 1), set (u8)thr_mecha_obj.unk_0083 to 1 = Setting mecha HACK to show GODZCD as GODZCDDA
0x73CAD8 ppc_emitter_eqv
 
0x73CAF0 ppc_emitter_mbar
0x2D: config_cmd_0x2D(u32 value2), store (u64)((value2 <<32) | value2) on *0x4002B4F0 and *0x4002B4F8
0x73CB08 ppc_emitter_divwuo
0x2E: store value2 on thr_mecha_obj.unk_002C
0x73CB20 ppc_emitter_divwu
0x2F: config_cmd_0x2F(value2); store (u32)value2 on *0x400AE784  SET_SPU2_PARAM 1 (same on deckard?)
0x73CB38 ppc_emitter_divwo
 
0x73CB50 ppc_emitter_divw
 
0x73CB68 ppc_emitter_divduo
 
0x73CB80 ppc_emitter_divdu
 
0x73CB98 ppc_emitter_unknown__divdo
 
0x73CBB0 ppc_emitter_divd
0x35: set "Force Flip Field" on = Similar usage like OPH flag Hack, but different approach.  
0x73CBC8 ppc_emitter_crclr
 
0x73CBE0 ppc_emitter_crorc
 
0x73CBF8 ppc_emitter_crmove
 
0x73CC10 ppc_emitter_crnot
 
0x73CC28 ppc_emitter_crnand
 
0x73CC40 ppc_emitter_crset
 
0x73CC58 ppc_emitter_crandc
 
0x73CC70 ppc_emitter_crand
0x3D: store (u32)value2 on UI_obj.unk_DC
0x73CC88 ppc_emitter_cntlzw
0x3E: set *0xB4A311 to 1
0x73CCA0 ppc_emitter_cntlzd
0x3F: config_cmd_0x3F(value2); store (u32)value2 on *0x4002B700
0x73CCB8 ppc_emitter_cmpwi
0x40: UI related, UI_285AC8(1) = store 1 on 0x402002F0 (alpha channel {blending})
0x73CCD0 ppc_emitter_cmpw
0x41: config_cmd_0x41(); set (u8)*0xB5B540 to 1
0x73CCE8 ppc_emitter_cmplwi
0x42: config_cmd_0x42(value2); repeat until ret 0,  todo...
0x73CD00 ppc_emitter_cmplw
-----------------------------------------------------------------------------------
0x73CD18 ppc_emitter_cmpldi
0x43: X = value2, or -1 if config end      value2 can be negative. -1 cause flickering in burnout2
0x73CD30 ppc_emitter_cmpld
      UI_285AC8(X); store (int32)X on *0x402002F0 (offset?) {{blending}}
0x73CD48 ppc_emitter_cmpdi
-----------------------------------------------------------------------------------
0x73CD60 ppc_emitter_cmpd
0x44: UI related, set UI_obj.flag_ED to 1, .set_sub_27AEE8(*obj_30700D0, 0) = *0x3172FD0 to 0 (smoothing)
0x73CD78 ppc_emitter_clrldi.
0x45: set (u8)*0x306F381 to 1
0x73CD90 ppc_emitter_clrldi
0x46: set (u8)*L2H_Impr to 1; "L2H Improvement" on
0x73CDA8 ppc_emitter_unknown
0x47: set (u8)*XOR_CSR_B5B378 to 1; "XOR CSR" on = XOR System Status Register
0x73CDC0 ppc_emitter_bnel
0x48: "VSYNC DELAY": store (u32)value2 on *vsync_delay_00 and (int32)value3 on *vsync_delay_04 //second value is int32, not uint32
0x73CDD8 ppc_emitter_bne
0x49: sub_49644(11, 0, 0), wait for (u32)0x40200420 = 0, than set (u32)0x40200424 to 0, (u64)0x40200428 to 0, (u32)0x40200420 to 11
0x73CDF0 ppc_emitter_bltl
0x4A: set: 0x40182D14, 0x40182D20, 0x40182D24, 0x40182D28 and 0x40182D2C to (u32)0x15100   
0x73CE08 ppc_emitter_blt
-----------------------------------------------------------------------------------
0x73CE20 ppc_emitter_blr
0x4B: save path related
0x73CE38 ppc_emitter_bla
      if next offset == end of config: set *cnf_cur_offset to next offset + 0x10
0x73CE50 ppc_emitter_bl
      value1(cmd, 0x4B)
0x73CE68 ppc_emitter_bgtl
     
0x73CE80 ppc_emitter_bgt
      gesammt 0x10
0x73CE98 ppc_emitter_beql
      u32 value2(r3);
0x73CEB0 ppc_emitter_beq
      u32 *value3(*string, ?);
0x73CEC8 ppc_emitter_bctrl
     
0x73CEE0 ppc_emitter_bctr
-----------------------------------------------------------------------------------
0x73CEF8 ppc_emitter_bdnzflrl
0x4C: iso.bin.enc related
0x73CF10 ppc_emitter_bdnzflr
      value2, value3(mode 1, 2, 3) = CD, DVD5, DVD9?
0x73CF28 ppc_emitter_bdnzfla
-----------------------------------------------------------------------------------
0x73CF40 ppc_emitter_bdnzfl
0x4D: X = value2, or -1 if config end
0x73CF58 ppc_emitter_bcctrl
      sub_49644(12, X, 0), wait for (u32)0x40200420 = 0, than set (u32)0x40200424 to X, (u64)0x40200428 to 0, (u32)0x40200420 to 12
0x73CF70 ppc_emitter_bcctr
-----------------------------------------------------------------------------------
0x73CF88 ppc_emitter_vsum4ubs
 
0x73CFA0 ppc_emitter_vsum4shs
 
0x73CFB8 ppc_emitter_vsum4sbs
0x50: config_cmd_0x50(), set (u8)*0x2456610 to 1
0x73CFD0 ppc_emitter_vsum2sws
0x73CFE8 ppc_emitter_vsubuws
0x73D000 ppc_emitter_vsubuwm
0x73D018 ppc_emitter_vsubuhs
0x73D030 ppc_emitter_vsubuhm
0x73D048 ppc_emitter_vsububs
0x73D060 ppc_emitter_vsububm
0x73D078 ppc_emitter_vsubsws
0x73D090 ppc_emitter_vsubshs
0x73D0A8 ppc_emitter_vsubsbs
0x73D0C0 ppc_emitter_vsubfp
0x73D0D8 ppc_emitter_vsubcuw
0x73D0F0 ppc_emitter_vsrw
0x73D108 ppc_emitter_vsro
0x73D120 ppc_emitter_vsrh
0x73D138 ppc_emitter_vsrb
0x73D150 ppc_emitter_vsraw
0x73D168 ppc_emitter_vsrah
0x73D180 ppc_emitter_vsrab
0x73D198 ppc_emitter_vsr
0x73D1B0 ppc_emitter_vspltw
0x73D1C8 ppc_emitter_vspltisw
0x73D1E0 ppc_emitter_vspltish
0x73D1F8 ppc_emitter_vspltisb
0x73D210 ppc_emitter_vsplth
0x73D228 ppc_emitter_vspltb
0x73D240 ppc_emitter_vslw
0x73D258 ppc_emitter_vslo
0x73D270 ppc_emitter_vslh
0x73D288 ppc_emitter_vxor
0x73D2A0 ppc_emitter_vupklsh
0x73D2B8 ppc_emitter_vupklsb
0x73D2D0 ppc_emitter_vupklpx
0x73D2E8 ppc_emitter_vupkhsh
0x73D300 ppc_emitter_vupkhsb
0x73D318 ppc_emitter_vupkhpx
0x73D330 ppc_emitter_vsumsws
0x73D348 ppc_emitter_xoris
0x73D360 ppc_emitter_xori_xnop
0x73D378 ppc_emitter_xor
0x73D390 ppc_emitter_unk_0x04000000(debug_trap)
0x73D3A8 ppc_emitter_adde
0x73D3C0 ppc_emitter_adde__
0x73D3D8 ppc_emitter_addco
0x73D3F0 ppc_emitter_addc
0x73D408 ppc_emitter_bdnzfa
0x73D420 ppc_emitter_bdnzf
0x73D438 ppc_emitter_ba
0x73D450 ppc_emitter_b
0x73D468 ppc_emitter_andis.
0x73D480 ppc_emitter_andi.
0x73D498 ppc_emitter_andc
0x73D4B0 ppc_emitter_and
0x73D4C8 ppc_emitter_addzeo
0x73D4E0 ppc_emitter_addze
0x73D4F8 ppc_emitter_addo
0x73D510 ppc_emitter_addmeo
0x73D528 ppc_emitter_addme
0x73D540 ppc_emitter_lis
0x73D558 ppc_emitter_addic
0x73D570 ppc_emitter_li
0x73D588 ppc_emitter_vsldoi
0x73D5A0 ppc_emitter_vslb
0x73D5B8 ppc_emitter_vsl
0x73D5D0 ppc_emitter_vsel
0x73D5E8 ppc_emitter_vrsqrtefp
0x73D600 ppc_emitter_vrlw
0x73D618 ppc_emitter_vrlh
0x73D630 ppc_emitter_vrlb
0x73D648 ppc_emitter_vlogefp
0x73D660 ppc_emitter_vlogefp__
0x73D678 ppc_emitter_vlogefp___
0x73D690 ppc_emitter_vlogefp____
0x73D6A8 ppc_emitter_vrefp
0x73D6C0 ppc_emitter_vpkuwus
0x73D6D8 ppc_emitter_vpkuwum
0x73D6F0 ppc_emitter_vpkuhus
0x73D708 ppc_emitter_vpkuhum
0x73D720 ppc_emitter_vpkswus
0x73D738 ppc_emitter_vpkswss
0x73D750 ppc_emitter_vpkshus
0x73D768 ppc_emitter_vpkshss
0x73D780 ppc_emitter_vpkpx
0x73D798 ppc_emitter_vperm
0x73D7B0 ppc_emitter_vmr_vor
0x73D7C8 ppc_emitter_vnot
0x73D7E0 ppc_emitter_vnmsubfp
0x73D7F8 ppc_emitter_vmulouh
0x73D810 ppc_emitter_vmuloub
0x73D828 ppc_emitter_vmulosh
0x73D840 ppc_emitter_vmulouw
0x73D858 ppc_emitter_vmuleuh
0x73D870 ppc_emitter_vmuleub
0x73D888 ppc_emitter_vmulesh
0x73D8A0 ppc_emitter_vmulesb
0x73D8B8 ppc_emitter_vmsumuhm
0x73D8D0 ppc_emitter_vmsumubm
0x73D8E8 ppc_emitter_vmsumshs
0x73D900 ppc_emitter_vmsumshm
0x73D918 ppc_emitter_vmsumuhs
0x73D930 ppc_emitter_vmsummbm
0x73D948 ppc_emitter_vmrglw
0x73D960 ppc_emitter_vmrglh
0x73D978 ppc_emitter_vmrglb
0x73D990 ppc_emitter_vmrghw
0x73D9A8 ppc_emitter_vmrghh
0x73D9C0 ppc_emitter_vmrghb
0x73D9D8 ppc_emitter_vmladduhm
0x73D9F0 ppc_emitter_vminuw
0x73DA08 ppc_emitter_vminuh
0x73DA20 ppc_emitter_vminub
0x73DA38 ppc_emitter_vminsw
0x73DA50 ppc_emitter_vminsh
0x73DA68 ppc_emitter_vminsb
0x73DA80 ppc_emitter_vminfp
0x73DA98 ppc_emitter_vmhraddshs
0x73DAB0 ppc_emitter_vmhaddshs
0x73DAC8 ppc_emitter_vmaxuw
0x73DAE0 ppc_emitter_vmaxuh
0x73DAF8 ppc_emitter_vmaxub
0x73DB10 ppc_emitter_vmaxsw
0x73DB28 ppc_emitter_vmaxsh
0x73DB40 ppc_emitter_vmaxsb
0x73DB58 ppc_emitter_vmaxfp
0x73DB70 ppc_emitter_vmaddfp
0x73DB88 ppc_emitter_vlogefp_
0x73DBA0 ppc_emitter_vexptefp
0x73DBB8 ppc_emitter_vctuxs
0x73DBD0 ppc_emitter_vctsxs
0x73DBE8 ppc_emitter_vcmpgtuw.
0x73DC00 ppc_emitter_vcmpgtuw
0x73DC18 ppc_emitter_vcmpgtuh.
0x73DC30 ppc_emitter_vcmpgtuh
0x73DC48 ppc_emitter_vcmpgtub.
0x73DC60 ppc_emitter_vcmpgtub
0x73DC78 ppc_emitter_vcmpgtsw.
0x73DC90 ppc_emitter_vcmpgtsw
0x73DCA8 ppc_emitter_vcmpgtsh.
0x73DCC0 ppc_emitter_vcmpgtsh
0x73DCD8 ppc_emitter_vcmpgtsb.
0x73DCF0 ppc_emitter_vcmpgtsb
0x73DD08 ppc_emitter_vcmpgtfp.
0x73DD20 ppc_emitter_vcmpgtfp
0x73DD38 ppc_emitter_vcmpgefp.
0x73DD50 ppc_emitter_vcmpgefp
0x73DD68 ppc_emitter_vcmpequw.
0x73DD80 ppc_emitter_vcmpequw
0x73DD98 ppc_emitter_vcmpequh.
0x73DDB0 ppc_emitter_vcmpequh
0x73DDC8 ppc_emitter_vcmpequb.
0x73DDE0 ppc_emitter_vcmpequb
0x73DDF8 ppc_emitter_vcmpeqfp.
0x73DE10 ppc_emitter_vcmpeqfp
0x73DE28 ppc_emitter_vcmpbfp.
0x73DE40 ppc_emitter_vcmpbfp
0x73DE58 ppc_emitter_vcfux
0x73DE70 ppc_emitter_vcfsx
0x73DE88 ppc_emitter_vavguw
0x73DEA0 ppc_emitter_vavguh
0x73DEB8 ppc_emitter_vavgub
0x73DED0 ppc_emitter_vavgsw
0x73DEE8 ppc_emitter_vavgsh
0x73DF00 ppc_emitter_vavgsb
0x73DF18 ppc_emitter_vandc
0x73DF30 ppc_emitter_vand
0x73DF48 ppc_emitter_vadduws
0x73DF60 ppc_emitter_vadduwm
0x73DF78 ppc_emitter_vadduhs
0x73DF90 ppc_emitter_vadduhm
0x73DFA8 ppc_emitter_vaddcuw
0x73DFC0 ppc_emitter_vaddubs
0x73DFD8 ppc_emitter_vaddubm
0x73DFF0 ppc_emitter_vaddsws
0x73E008 ppc_emitter_vaddshs
0x73E020 ppc_emitter_vaddsbs
0x73E038 ppc_emitter_vaddfp
0x73E050 ppc_emitter_twi
0x73E068 ppc_emitter_tw
0x73E080 ppc_emitter_tdi
0x73E098 ppc_emitter_td
0x73E0B0 ppc_emitter_sync
0x73E0C8 ppc_emitter_subfzeo
0x73E0E0 ppc_emitter_subfze
0x73E0F8 ppc_emitter_subfo
0x73E110 ppc_emitter_subfmeo
0x73E128 ppc_emitter_subfme
0x73E140 ppc_emitter_subfic
0x73E158 ppc_emitter_subfe
0x73E170 ppc_emitter_subfe_
0x73E188 ppc_emitter_subfco.
0x73E1A0 ppc_emitter_subfco
0x73E1B8 ppc_emitter_subfc
0x73E1D0 ppc_emitter_subf
0x73E1E8 ppc_emitter_stwx
0x73E200 ppc_emitter_stwu
0x73E218 ppc_emitter_stwbrx
0x73E230 ppc_emitter_stw
0x73E248 ppc_emitter_stvxl
0x73E260 ppc_emitter_stvx
0x73E278 ppc_emitter_stvewx
0x73E290 ppc_emitter_stvehx
0x73E2A8 ppc_emitter_stvebx
0x73E2C0 ppc_emitter_sthx
0x73E2D8 ppc_emitter_sthu
0x73E2F0 ppc_emitter_sthbrx
0x73E308 ppc_emitter_sth
0x73E320 ppc_emitter_stfsx
0x73E338 ppc_emitter_stfsux
0x73E350 ppc_emitter_stfs
0x73E368 ppc_emitter_stfiwx
0x73E380 ppc_emitter_stfdx
0x73E398 ppc_emitter_stfd
0x73E3B0 ppc_emitter_stdx
0x73E3C8 ppc_emitter_stdbrx
0x73E3E0 ppc_emitter_std
0x73E3F8 ppc_emitter_stbx
0x73E410 ppc_emitter_stbu
0x73E428 ppc_emitter_stb
0x73E440 ppc_emitter_srw
0x73E458 ppc_emitter_srd
0x73E470 ppc_emitter_srawi
0x73E488 ppc_emitter_sraw
0x73E4A0 ppc_emitter_sradi
0x73E4B8 ppc_emitter_srad
0x73E4D0 ppc_emitter_slw
0x73E4E8 ppc_emitter_sld
0x73E500 ppc_emitter_rlwnm_31
0x73E518 ppc_emitter_rotld
0x73E530 ppc_emitter_rlwnm_0
0x73E548 ppc_emitter_clrrwi_31
0x73E560 ppc_emitter_rlwimi
0x73E578 ppc_emitter_insrdi_64
0x73E590 ppc_emitter_clrrdi
0x73E5A8 ppc_emitter_clrldi_0
0x73E5C0 ppc_emitter_clrldi_0__
0x73E5D8 ppc_emitter_clrlsldi
0x73E5F0 ppc_emitter_rldcr
0x73E608 ppc_emitter_rotld_
0x73E620 ppc_emitter_sync_
0x73E638 ppc_emitter_oris
0x73E650 ppc_emitter_ori
0x73E668 ppc_emitter_orc
0x73E680 ppc_emitter_mr_or
0x73E698 ppc_emitter_not
0x73E6B0 ppc_emitter_neg
0x73E6C8 ppc_emitter_neg_
0x73E6E0 ppc_emitter_nand
0x73E6F8 ppc_emitter_mullwo
0x73E710 ppc_emitter_mullw
0x73E728 ppc_emitter_mulli
0x73E740 ppc_emitter_mulldo
0x73E758 ppc_emitter_mulld
0x73E770 ppc_emitter_mulhwu
0x73E788 ppc_emitter_li_
0x73E7A0 ppc_emitter_clrldi__
0x73E7B8 ppc_emitter_subf_
0x73E7D0 ppc_emitter_clrrdi_63
0x73E7E8 ppc_emitter_clrrdi_63_
0x73E800 ppc_emitter_clrrwi
0x73E818 ppc_emitter_clrlwi_0
0x73E830 ppc_emitter_clrlwi_0_
</pre>
</pre>


===ps2_gxemu ppu emitter by opd (4.75?)===
===Known supported instructions===
 
Mips instructions supported by ps2_netemu. Probably there are more, here are just currently known. (thx to 3141card)
 
*ABS
*ADD
*ADDA
*ADDAI
*ADDAQ
*ADDAW
*ADDAX
*ADDAY
*ADDAZ
*ADDI
*ADDQ
*ADDW
*ADDX
*ADDY
*ADDZ
*B
*BAL
*CLIP
*DIV
*FCAND
*FCEQ
*FCGET
*FCOR
*FCSET
*FMAND
*FMEQ
*FMOR
*FSAND
*FSEQ
*FSOR
*FSSET
*FTOI0
*FTOI15
*FTOI4
*IADD
*IADDI
*IADDIU
*IAND
*IBEQ
*IBGEZ
*IBGTZ
*IBLEZ
*IBLTZ
*IBNE
*ILW
*ILWR
*IOR
*ISUB
*ISUBIU
*ISW
*ISWR
*ITOF0
*ITOF12
*ITOF15
*ITOF4
*JALR
*JR
*LQ
*LQD
*LQI
*MADD
*MADDA
*MADDAI
*MADDAQ
*MADDAW
*MADDAX
*MADDAY
*MADDAZ
*MADDI
*MADDQ
*MADDW
*MADDX
*MADDY
*MADDZ
*MAX
*MAXI
*MAXW
*MAXX
*MAXY
*MAXZ
*MFIR
*MINI
*MINII
*MINIW
*MINIX
*MINIY
*MINIZ
*MOVE
*MR32
*MSUB
*MSUBA
*MSUBAI
*MSUBAQ
*MSUBAW
*MSUBAX
*MSUBAY
*MSUBAZ
*MSUBI
*MSUBQ
*MSUBW
*MSUBX
*MSUBY
*MSUBZ
*MTIR
*MUL
*MULA
*MULAI
*MULAQ
*MULAW
*MULAX
*MULAY
*MULAZ
*MULI
*MULQ
*MULW
*MULX
*MULY
*MULZ
*NOP
*OPMSUB
*OPMULA
*RGET
*RINIT
*RNEXT
*RSQRT
*RXOR
*SQ
*SQD
*SQI
*SQRT
*SUB
*SUBA
*SUBAI
*SUBAQ
*SUBAW
*SUBAX
*SUBAY
*SUBAZ
*SUBI
*SUBQ
*SUBW
*SUBX
*SUBY
*SUBZ
*WAITQ
*XITOP
 
 
===clamping===
 
PS3 CELL is full IEEE 754 compliant only with PPE/PPU part. SPE/SPU is compliant with IEEE 754 only in double precision, while single precision round-towards-zero instead of round-towards-even. PS2 is not IEEE 754 compliant at all. In summary is still not clear that FPU clamping is needed and used in ps2_netemu, but probably not.
 
To do:
https://gcc.gnu.org/ml/gcc-patches/2013-07/msg00231.html
"This is the case on the PS2 and the PS3. For example inf minus inf should be NaN, but on both systems it is 0. I tested it on r5900 and the PS3 SPU." Seems to confirm above.
 
===fpu/cop2 accuracy===
 
To do
 
* --fpu-accurate-addsub-range
* --fpu-accurate-muldiv-range
* --cop2-accurate-mul-range
* --cop2-accurate-addsub-range
 
* 0x0E - Same as 0x0F but not used per range
* 0x0F
* 0x10 - Massive slow down while used at full game memory range. BR2
* 0x26 ADD/SUB accu (Also for float)
* 0x27 COP2 Accu (confirmed)
 
====0x10====
 
Weird usage, include floats, cop2 advanced operations, converting double to single precision floating-point. There is small possibility that is overall accuracy command. Just like interpreter mode from pcsx2, but range based.
 
====0x27====
 
Example code where Sony used command (with commands comment):
 
<pre>
<pre>
0x6557D0  ppu_emitter_xoris
0x3476F8                cop2    0x1CC09BC        # vmulax.xyz ACC,vf01,vf12x
0x6557E8  ppu_emitter_srwi
0x3476FC                cop2    0x1CC10BD        # vmadday.xyz ACC,vf02,vf12y
0x655800  ppu_emitter_slwi
0x347700                cop2    0x1CC1B8A        # vmaddz.xyz vf14, vf03, vf12z
0x655818  sub_101FBC
0x347704                cop2    0x1E409BC        # vmulax.xyzw ACC,vf01,vf04x
0x655830  ppu_emitter_extrwi_unconfirmed_____todo
0x347708                cop2    0x1E410BD        # vmadday.xyzw ACC,vf02,vf04y
0x655848  ppu_emitter_sldi
0x34770C                cop2    0x1E419CA        # vmaddz.xyzw vf07, vf03, vf04z
0x655860  ppu_emitter_extldi
0x347710                cop2    0x1CB739B        # vmulw.xyz vf14,vf14,vf11w
0x655878  ppu_emitter_subf_____todo (used only in visub)
0x347714                cop2    0x1E509BC        # vmulax.xyzw ACC,vf01,vf05x
0x655890  ppu_emitter_srdi
0x347718                cop2    0x1E510BD        # vmadday.xyzw ACC,vf02,vf05y
0x6558A8  ppu_emitter_li
0x34771C                cop2    0x1E51A0A        # vmaddz.xyzw vf08, vf03, vf05z
0x6558C0  ppu_emitter_add
0x347720                cop2    0x1CB7368        # vadd.xyz vf13, vf14, vf11
0x6558D8  ppu_emitter_addc
0x347724                cop2    0x1E609BC        # vmulax.xyzw ACC,vf01,vf06x
0x6558F0  ppu_emitter_addco
0x347728                cop2    0x1E610BD        # vmadday.xyzw ACC,vf02,vf06y
0x655908  ppu_emitter_adde
0x34772C                cop2    0x1E61A4A        # vmaddz.xyzw vf09, vf03, vf06z
0x655920  ppu_emitter_adde_____todo
0x655938  ppu_emitter_addi
0x655950  ppu_emitter_addic
0x655968  ppu_emitter_lis
0x655980  ppu_emitter_addme
0x655998  ppu_emitter_addmeo
0x6559B0  ppu_emitter_addo
0x6559C8  ppu_emitter_addze
0x6559E0  ppu_emitter_addzeo
0x6559F8  ppu_emitter_and
0x655A10  ppu_emitter_andc
0x655A28  ppu_emitter_andi.
0x655A40  ppu_emitter_andis.
0x655A58  ppu_emitter_b
0x655A70  ppu_emitter_ba
0x655A88  ppu_emitter_bdnzf
0x655AA0  ppu_emitter_bdnzfa
0x655AB8  ppu_emitter_bcctr
0x655AD0  ppu_emitter_bcctrl
0x655AE8  ppu_emitter_bdnzfl
0x655B00  ppu_emitter_bdnzfla
0x655B18  ppu_emitter_bdnzflr
0x655B30  ppu_emitter_bdnzflrl
0x655B48  ppu_emitter_bctr
0x655B60  ppu_emitter_bctrl
0x655B78  ppu_emitter_beq
0x655B90  ppu_emitter_beql
0x655BA8  ppu_emitter_bgt
0x655BC0  ppu_emitter_bgtl
0x655BD8  ppu_emitter_bl
0x655BF0  ppu_emitter_bla
0x655C08  ppu_emitter_blr
0x655C20  ppu_emitter_blt
0x655C38  ppu_emitter_bltl
0x655C50  ppu_emitter_bne
0x655C68  ppu_emitter_bnel
0x655C80  ppu_emitter_unk_used_in_r5900_break
0x655C98  ppu_emitter_clrldi
0x655CB0  ppu_emitter_clrldi.
0x655CC8  ppu_emitter_cmpd
0x655CE0  ppu_emitter_cmpdi
0x655CF8  ppu_emitter_cmpld
0x655D10  ppu_emitter_cmpldi
0x655D28  ppu_emitter_cmplw
0x655D40  ppu_emitter_cmplwi
0x655D58  ppu_emitter_cmpw
0x655D70  ppu_emitter_cmpwi
0x655D88  ppu_emitter_cntlzd
0x655DA0  ppu_emitter_cntlzw
0x655DB8  ppu_emitter_crand
0x655DD0  ppu_emitter_crandc
0x655DE8  ppu_emitter_crset
0x655E00  ppu_emitter_crnand
0x655E18  ppu_emitter_crnot
0x655E30  ppu_emitter_crmove
0x655E48  ppu_emitter_crorc
0x655E60  ppu_emitter_crclr
0x655E78  ppu_emitter_divd
0x655E90  ppu_emitter_divdo
0x655EA8  ppu_emitter_divdu
0x655EC0  ppu_emitter_divduo
0x655ED8  ppu_emitter_divw
0x655EF0  ppu_emitter_divwo
0x655F08  ppu_emitter_divwu
0x655F20  ppu_emitter_divwuo
0x655F38  ppu_emitter_mbar
0x655F50  ppu_emitter_eqv
0x655F68  ppu_emitter_extsb
0x655F80  ppu_emitter_extsh
0x655F98  ppu_emitter_extsw
0x655FB0  ppu_emitter_fabs
0x655FC8  ppu_emitter_fadd
0x655FE0  ppu_emitter_fadds
0x655FF8  ppu_emitter_fcfid
0x656010  ppu_emitter_fcmpo
0x656028  ppu_emitter_fcmpu
0x656040  ppu_emitter_fctid
0x656058  ppu_emitter_fctidz
0x656070  ppu_emitter_fctiw
0x656088  ppu_emitter_fctiwz
0x6560A0  ppu_emitter_fdiv
0x6560B8  ppu_emitter_fdivs
0x6560D0  ppu_emitter_fmadd
0x6560E8  ppu_emitter_fmadds
0x656100  ppu_emitter_fmr
0x656118  ppu_emitter_fmsub
0x656130  ppu_emitter_fmsubs
0x656148  ppu_emitter_fmul
0x656160  ppu_emitter_fmuls
0x656178  ppu_emitter_fnabs
0x656190  ppu_emitter_fneg
0x6561A8  ppu_emitter_fnmadd
0x6561C0  ppu_emitter_fnmadds
0x6561D8  ppu_emitter_fsub_with_4_regs
0x6561F0  ppu_emitter_fnmsubs
0x656208  ppu_emitter_fres
0x656220  ppu_emitter_frsp
0x656238  ppu_emitter_frsqrte
0x656250  ppu_emitter_fsel
0x656268  ppu_emitter_fsqrt
0x656280  ppu_emitter_fsqrts
0x656298  ppu_emitter_fsub
0x6562B0  ppu_emitter_fsubs
0x6562C8  ppu_emitter_isync
0x6562E0  ppu_emitter_lb
0x6562F8  ppu_emitter_lbzu
0x656310  ppu_emitter_lbzx
0x656328  ppu_emitter_ld
0x656340  ppu_emitter_ldbrx
0x656358  ppu_emitter_ldx
0x656370  ppu_emitter_lfd
0x656388  ppu_emitter_lfdx
0x6563A0  ppu_emitter_lfs
0x6563B8  ppu_emitter_lfsx
0x6563D0  ppu_emitter_lhbrx
0x6563E8  ppu_emitter_lhz
0x656400  ppu_emitter_lhzu
0x656418  ppu_emitter_lhzx
0x656430  ppu_emitter_lvebx
0x656448  ppu_emitter_lvehx
0x656460  ppu_emitter_lvewx
0x656478  ppu_emitter_lvlx
0x656490  ppu_emitter_lvsl
0x6564A8  ppu_emitter_lvsr
0x6564C0  ppu_emitter_lvx
0x6564D8  ppu_emitter_lvxl
0x6564F0  ppu_emitter_lwbrx
0x656508  ppu_emitter_lwsync
0x656520  ppu_emitter_lwz
0x656538  ppu_emitter_lwzu
0x656550  ppu_emitter_lwzx
0x656568  ppu_emitter_mfcr
0x656580  ppu_emitter_mfctr
0x656598  ppu_emitter_mflr
0x6565B0  ppu_emitter_mfocrf
0x6565C8  ppu_emitter_mftb
0x6565E0  ppu_emitter_mfvscr
0x6565F8  ppu_emitter_mtcrf
0x656610  ppu_emitter_mtctr
0x656628  ppu_emitter_mtlr
0x656640  ppu_emitter_mtocrf
0x656658  ppu_emitter_mtvscr
0x656670  ppu_emitter_mullhd
0x656688  ppu_emitter_mullhdu
0x6566A0  ppu_emitter_mullhw
0x6566B8  ppu_emitter_mullhwu
0x6566D0  ppu_emitter_mulld
0x6566E8  ppu_emitter_mulldo
0x656700  ppu_emitter_mulli
0x656718  ppu_emitter_mullw
0x656730  ppu_emitter_mullwo
0x656748  ppu_emitter_nand
0x656760  ppu_emitter_neg
0x656778  ppu_emitter_neg__________todo
0x656790  ppu_emitter_nor
0x6567A8  ppu_emitter_or
0x6567C0  ppu_emitter_orc
0x6567D8  ppu_emitter_ori
0x6567F0  ppu_emitter_oris
0x656808  ppu_emitter_ptesync
0x656820  ppu_emitter_rldcl
0x656838  ppu_emitter_rldcr
0x656850  ppu_emitter_rldir
0x656868  ppu_emitter_rldicl
0x656880  ppu_emitter_rldicl___________todo
0x656898  ppu_emitter_rldicr
0x6568B0  ppu_emitter_rldimi
0x6568C8  ppu_emitter_rlwimi
0x6568E0  ppu_emitter_rlwinm
0x6568F8  ppu_emitter_rlwnm
0x656910  ppu_emitter_rotld
0x656928  ppu_emitter_rlwnm_mb31
0x656940  ppu_emitter_sld
0x656958  ppu_emitter_slw
0x656970  ppu_emitter_srad
0x656988  ppu_emitter_sradi
0x6569A0  ppu_emitter_sraw
0x6569B8  ppu_emitter_srawi
0x6569D0  ppu_emitter_srd
0x6569E8  ppu_emitter_srw
0x656A00  ppu_emitter_stb
0x656A18  ppu_emitter_stbu
0x656A30  ppu_emitter_stbx
0x656A48  ppu_emitter_std
0x656A60  ppu_emitter_stdbrx
0x656A78  ppu_emitter_stdx
0x656A90  ppu_emitter_stfd
0x656AA8  ppu_emitter_stfdx
0x656AC0  ppu_emitter_stfiwx
0x656AD8  ppu_emitter_stfs
0x656AF0  ppu_emitter_stfsux
0x656B08  ppu_emitter_stfsx
0x656B20  ppu_emitter_sth
0x656B38  ppu_emitter_sthbrx
0x656B50  ppu_emitter_sthu
0x656B68  ppu_emitter_sthx
0x656B80  ppu_emitter_stvebx
0x656B98  ppu_emitter_stvehx
0x656BB0  ppu_emitter_stvewx
0x656BC8  ppu_emitter_stvx
0x656BE0  ppu_emitter_stvxl
0x656BF8  ppu_emitter_stw
0x656C10  ppu_emitter_stwbrx
0x656C28  ppu_emitter_stwu
0x656C40  ppu_emitter_stwx
0x656C58  ppu_emitter_subf
0x656C70  ppu_emitter_subfc
0x656C88  ppu_emitter_subfco
0x656CA0  ppu_emitter_subfco.
0x656CB8  ppu_emitter_subfe
0x656CD0  ppu_emitter_subfe________todo
0x656CE8  ppu_emitter_subfic
0x656D00  ppu_emitter_subfme
0x656D18  ppu_emitter_subfmeo
0x656D30  ppu_emitter_subfo
0x656D48  ppu_emitter_subfze
0x656D60  ppu_emitter_subfzeo
0x656D78  ppu_emitter_sync
0x656D90  ppu_emitter_td
0x656DA8  ppu_emitter_tdi
0x656DC0  ppu_emitter_tw
0x656DD8  ppu_emitter_twi
0x656DF0  ppu_emitter_vaddfp
0x656E08  ppu_emitter_vaddsbs
0x656E20  ppu_emitter_vaddshs
0x656E38  ppu_emitter_vaddsws
0x656E50  ppu_emitter_vaddubm
0x656E68  ppu_emitter_vaddubs
0x656E80  ppu_emitter_vaddcuw
0x656E98  ppu_emitter_vadduhm
0x656EB0  ppu_emitter_vadduhs
0x656EC8  ppu_emitter_vadduwm
0x656EE0  ppu_emitter_vadduws
0x656EF8  ppu_emitter_vand
0x656F10  ppu_emitter_vandc
0x656F28  ppu_emitter_vavgsb
0x656F40  ppu_emitter_vavgsh
0x656F58  ppu_emitter_vavgsw
0x656F70  ppu_emitter_vavgub
0x656F88  ppu_emitter_vavguh
0x656FA0  ppu_emitter_vavguw
0x656FB8  ppu_emitter_vcfsx
0x656FD0  ppu_emitter_vcfux
0x656FE8  ppu_emitter_vcmpbfp
0x657000  ppu_emitter_vcmpbfp.
0x657018  ppu_emitter_vcmpeqfp
0x657030  ppu_emitter_vcmpeqfp.
0x657048  ppu_emitter_vcmpequb
0x657060  ppu_emitter_vcmpequb.
0x657078  ppu_emitter_vcmpequh
0x657090  ppu_emitter_vcmpequh.
0x6570A8  ppu_emitter_vcmpequw
0x6570C0  ppu_emitter_vcmpequw.
0x6570D8  ppu_emitter_vcmpgefp
0x6570F0  ppu_emitter_vcmpgefp.
0x657108  ppu_emitter_vcmpgtfp
0x657120  ppu_emitter_vcmpgtfp.
0x657138  ppu_emitter_vcmpgtsb
0x657150  ppu_emitter_vcmpgtsb.
0x657168  ppu_emitter_vcmpgtsh
0x657180  ppu_emitter_vcmpgtsh.
0x657198  ppu_emitter_vcmpgtsw
0x6571B0  ppu_emitter_vcmpgtsw.
0x6571C8  ppu_emitter_vcmpgtub
0x6571E0  ppu_emitter_vcmpgtub.
0x6571F8  ppu_emitter_vcmpgtuh
0x657210  ppu_emitter_vcmpgtuh.
0x657228  ppu_emitter_vcmpgtuw
0x657240  ppu_emitter_vcmpgtuw.
0x657258  ppu_emitter_vctsxs
0x657270  ppu_emitter_vctuxs
0x657288  ppu_emitter_vexptefp
0x6572A0  ppu_emitter_vlogefp
0x6572B8  ppu_emitter_vmaddfp
0x6572D0  ppu_emitter_vmaxfp
0x6572E8  ppu_emitter_vmaxsb
0x657300  ppu_emitter_vmaxsh
0x657318  ppu_emitter_vmaxsw
0x657330  ppu_emitter_vmaxub
0x657348  ppu_emitter_vmaxuh
0x657360  ppu_emitter_vmaxuw
0x657378  ppu_emitter_vmhaddshs
0x657390  ppu_emitter_vmhraddshs
0x6573A8  ppu_emitter_vminfp
0x6573C0  ppu_emitter_vminsb
0x6573D8  ppu_emitter_vminsh
0x6573F0  ppu_emitter_vminsw
0x657408  ppu_emitter_vminub
0x657420  ppu_emitter_vminuh
0x657438  ppu_emitter_vminuw
0x657450  ppu_emitter_vmladduhm
0x657468  ppu_emitter_vmrghb
0x657480  ppu_emitter_vmrghh
0x657498  ppu_emitter_vmrghw
0x6574B0  ppu_emitter_vmrglb
0x6574C8  ppu_emitter_vmrglh
0x6574E0  ppu_emitter_vmrglw
0x6574F8  ppu_emitter_vmsummbm
0x657510  ppu_emitter_vmsumuhs
0x657528  ppu_emitter_vmsumshm
0x657540  ppu_emitter_vmsumshs
0x657558  ppu_emitter_vmsumubm
0x657570  ppu_emitter_vmsumuhm
0x657588  ppu_emitter_vmulesb
0x6575A0  ppu_emitter_vmulesh
0x6575B8  ppu_emitter_vmuleub
0x6575D0  ppu_emitter_vmuleuh
0x6575E8  ppu_emitter_vmulouw
0x657600  ppu_emitter_vmulosh
0x657618  ppu_emitter_vmuloub
0x657630  ppu_emitter_vmulouh
0x657648  ppu_emitter_vnmsubfp
0x657660  ppu_emitter_vnot
0x657678  ppu_emitter_vmr_vor
0x657690  ppu_emitter_vperm
0x6576A8  ppu_emitter_vpkpx
0x6576C0  ppu_emitter_vpkshss
0x6576D8  ppu_emitter_vpkshus
0x6576F0  ppu_emitter_vpkswss
0x657708  ppu_emitter_vpkswus
0x657720  ppu_emitter_vpkuhum
0x657738  ppu_emitter_vpkuhus
0x657750  ppu_emitter_vpkuwum
0x657768  ppu_emitter_vpkuwus
0x657780  ppu_emitter_vrefp
0x657798  ppu_emitter_vlogefp_
0x6577B0  ppu_emitter_vlogefp__
0x6577C8  ppu_emitter_vlogefp___
0x6577E0  ppu_emitter_vlogefp____
0x6577F8  ppu_emitter_vrlb
0x657810  ppu_emitter_vrlh
0x657828  ppu_emitter_vrlw
0x657840  ppu_emitter_vrsqrtefp
0x657858  ppu_emitter_vsel
0x657870  ppu_emitter_vsl
0x657888  ppu_emitter_vslb
0x6578A0  ppu_emitter_vsldoi
0x6578B8  ppu_emitter_vslh
0x6578D0  ppu_emitter_vslo
0x6578E8  ppu_emitter_vslw
0x657900  ppu_emitter_vspltb
0x657918  ppu_emitter_vsplth
0x657930  ppu_emitter_vspltisb
0x657948  ppu_emitter_vspltish
0x657960  ppu_emitter_vspltisw
0x657978  ppu_emitter_vspltw
0x657990  ppu_emitter_vsr
0x6579A8  ppu_emitter_vsrab
0x6579C0  ppu_emitter_vsrah
0x6579D8  ppu_emitter_vsraw
0x6579F0  ppu_emitter_vsrb
0x657A08  ppu_emitter_vsrh
0x657A20  ppu_emitter_vsro
0x657A38  ppu_emitter_vsrw
0x657A50  ppu_emitter_vsubcuw
0x657A68  ppu_emitter_vsubfp
0x657A80  ppu_emitter_vsubsbs
0x657A98  ppu_emitter_vsubshs
0x657AB0  ppu_emitter_vsubsws
0x657AC8  ppu_emitter_vsububm
0x657AE0  ppu_emitter_vsububs
0x657AF8  ppu_emitter_vsubuhm
0x657B10  ppu_emitter_vsubuhs
0x657B28  ppu_emitter_vsubuwm
0x657B40  ppu_emitter_vsubuws
0x657B58  ppu_emitter_vsum2sws
0x657B70  ppu_emitter_vsum4sbs
0x657B88  ppu_emitter_vsum4shs
0x657BA0  ppu_emitter_vsum4ubs
0x657BB8  ppu_emitter_vsumsws
0x657BD0  ppu_emitter_vupkhpx
0x657BE8  ppu_emitter_vupkhsb
0x657C00  ppu_emitter_vupkhsh
0x657C18  ppu_emitter_vupklpx
0x657C30  ppu_emitter_vupklsb
0x657C48  ppu_emitter_vupklsh
0x657C60  ppu_emitter_vxor
0x657C78  ppu_emitter_watchpoint
0x657C90  ppu_emitter_xor
0x657CA8  ppu_emitter_xori
</pre>
</pre>


===ps2_netemu vu1-to-spu emitter===
===DECKARD===
I need to clean this up little bit before posting on ps2 emu page. This is opd list of recompiler functions that are responsible for emitting vu1 to spu translated opcodes (so called VRC). #ToDo sub_xxx are unknown, or unused (so i was too lazy to look at them).
 
<pre>               
Since 750XX ps2 Sony abandoned using MIPS IOP chip, exchanging it to PowerPC 405GP chip. Here are some internal deckard settings to keep compatibility for ps2 titles on scph-750XX and later. We can safely assume that some of them are needed also on PS3, and are used in config tables.
0x736DD8 vu1_emitter_RB_RA_RT
 
0x736DF0 vu1_emitter_IMM_RA_RT imm - i10 or i7
{| class="wikitable sortable"
0x736E08 vu1_emitter_I8_RA_RT
|-
0x736E20 vu1_emitter_I16_RT # ilhu, iolh, fsmbi, il, ila
! deckard !! ps2_gxemu !! notes
0x736E38 sub_145834
|-
0x736E50 vu1_emitter_MFSPR_MTSPR
| PARAM_MDEC_DELAY_CYCLE ||  ||  PS1 Related?
0x736E68 sub_145934
|-
0x736E80 sub_14598C
| PARAM_SPU_INT_DELAY_LIMIT ||  || 
0x736E98 sub_1459EC
|-
0x736EB0 sub_145A30
| PARAM_SPU_INT_DELAY_PPC_COEFF ||  || 
0x736EC8 vu1_emitter_BRASL_0x8B00
|-
0x736EE0 vu1_emitter_AI_r57_r57_0x10
| PARAM_SPU2_INT_DELAY_LIMIT ||  SPU2_BEHAVIOR? || 
0x736EF8 vu1_emitter_UNK1
|-
0x736F10 vu1_emitter_LQD
| PARAM_SPU2_INT_DELAY_PPC_COEFF ||  SPU2_BEHAVIOR? || 
0x736F28 sub_145E8C
|-
0x736F40 sub_145F90
| PARAM_DMAC_CH10_INT_DELAY || DMAC_CH10_INT_DELAY  || 
0x736F58 sub_146060
|-
0x736F70 sub_14612C
| PARAM_CPU_DELAY || CPU_DELAY || 0x20? 
0x736F88 sub_1461D8
|-
0x736FA0 vu1_emitter_RT_RB_RA_RC
| PARAM_SPU_DMA_WAIT_LIMIT  ||  || 
0x736FB8 sub_146418
|-
0x736FD0 sub_146490
| PARAM_GPU_DMA_WAIT_LIMIT  ||  || 
0x736FE8 vu1_emitter_ORI
|-
0x737000 vu1_emitter_BRASL_0x8A80
| PARAM_DMAC_CH10_INT_DELAY_DPC ||  || 
0x737018 sub_1467B4
|-
0x737030 sub_1468EC
| PARAM_CPU_DELAY_DPC        ||  || 
0x737048 sub_1469AC
|-
0x737060 VU_REC_xgkick_146A6C
| PARAM_USB_DELAYED_INT_ENAB ||  || 
</pre>
|-
| PARAM_TIMER_LOAD_DELAY    ||  || 
|-
| PARAM_SIO0_DTR_SCK_DELAY  ||  || 
|-
| PARAM_SIO0_DSR_SCK_DELAY_C ||  || 
|-
| PARAM_SIO0_DSR_SCK_DELAY_M ||  || 
|-
| PARAM_MIPS_DCACHE_ON      ||  || 
|-
| PARAM_CACHE_FLASH_CHANNELS ||  ||
|-
|}
 
unsorted gxemu:
 
* "SIO2_MASK"
* "DEV9_MASK"
* "USB_MASK"
* "SIF_DMA_SYNC"
* "SIF_DMA_LOAD"
* "DMAC_CH10_INT_DELAY"
* "MECHA_RECOGTIME"
* "CPU_DELAY"
* "DEV5_INT_SPEED"
* "CDVD_READ_DELAY"
* "SPU2_BEHAVIOR"
 
PPC 405 chip documentation: https://www2.informatik.hu-berlin.de/~fwinkler/psvfpga/amirix/405_um.pdf
 
===Per game hooks 0x01===
 
There are some per game hooks in 0x01 netemu table not compatible with other games at all. Good example are GTA fixes, or triace hack. More coming soon™...
PS4 shows that hook commands sometimes are not even needed to make game run correctly. Sometimes there are commands related to fixing timing for new TV standard, sometime minor fixes. Looks like there are only few cases when hooks are fixing major issues. Anyway.. 90% 0x01 commands are per title ID fixes. Not really worth reversing, in most cases is just rewritten game function.
 
* 0x0A - Triace (0x4b1ed5e7 db prec? custom Addi rountime)
* 0x0B - Triace, interesting. Star Ocean don't need it
* 0x12 - Disney's Finding Nemo hook
* 0x13 - 0x16 - Snowblind hacks (custom name ;) )
* 0x1B - 0x1E - Street Racing Syndicate hook
* 0x1F - 0x22 - Ford vs. Chevy
* 0x0F - 0x11, and 0x3B doing the same but "probing" for conditions, and answering in different addresses
* 0x2F - 0x32 Singstar's hooks
 
===PS3 DDR USB Mat seems to work on ps2_netemu===
 
Discord chat:


===ps2_gxemu vu1-to-spu emitter===
I need to clean this up little bit before posting on ps2 emu page. This is opd list of recompiler functions that are responsible for emitting vu1 to spu translated opcodes (so called VRC). #ToDo sub_xxx are unknown, or unused (so i was too lazy to look at them).
<pre>
<pre>
0x6583F8  spu_emitter_stop_0x1234
Borey - Dziś o 16:25
0x658410  sub_146084
I have a PS3 Dance Dance Revolution mat, and it works fine with Dance Dance Revolution for the PS3, but when I try and use it on SuperNova(PS2) it won't recognize opposite arrows. (up and down, left and right) because I think the game doesn't recognize it as a mat, rather as a controller. Is there any software I can use to trick the game to thinking there's a mat connected?
0x658428  spu_emitter_brasl_0x8B00_xgkick
Kozarovv - Dziś o 16:26
0x658440  spu_emitter_ai_r57_r57_0x10
@Borey Do any "button" on map work at all in ps2 version?
0x658458  spu_emitter_rt_rb_ra_rc
*mat
0x658470  spu_emitter_rb_ra_rt
Borey - Dziś o 16:26
0x658488 sub_146568
Yes.
0x6584A0  sub_146670
You can play the game, just can't touch opposite arrows.
0x6584B8  spu_emitter_i16_rt
Which is impossible cause there is jump arrows.
0x6584D0  spu_emitter_brasl_efu_helpers___todo
No up and down, no left or right.
0x6584E8  spu_emitter_brasl_efu_helpers
Kozarovv - Dziś o 16:27
0x658500  sub_1469AC
Interesting. What is your ps3 model?
0x658518  sub_146A88
Borey - Dziś o 16:27
0x658530  sub_146B6C
I think it's because the mat is inputting D-Pad controls.
0x658548  sub_146C74
So you can't press both, like on a controller.
0x658560  sub_146D94
Let me look really quick.
0x658578  sub_146EB4
Kozarovv - Dziś o 16:27
0x658590  spu_emitter_binz_r60_r62_______todo_more
Or just tell me that is FAT model?
0x6585A8  spu_emitter_move_r53_r54
Or any slim/superslim?
0x6585C0  spu_emitter_move_r55_r56
cikeZ00 - Dziś o 16:28
0x6585D8  sub_1472CC
RIP
0x6585F0  sub_1473B0
Kozarovv - Dziś o 16:28
0x658608  spu_emitter_brasl_0x8A80
Is really weird that mat work for you at all, when you are in ps2 emu
Borey - Dziś o 16:29
CECH-2001A
Kozarovv - Dziś o 16:29
Mat is usb, or bluetooth?
Borey - Dziś o 16:29
USB.
Original PS3 mat.
https://www.amazon.com/gp/product/B004JATP2Q/ref=oh_aui_detailpage_o00_s00?ie=UTF8&psc=1
DeViL303 - Dziś o 16:30
interesting..we need a dev to buy one of those and work it out.
Borey - Dziś o 16:30
Well.
Is there a button remapper app anyone knows about?
I can just map up and down to square and triangle
So it'll work fine.
Cause I'm convinced SuperNova thinks the mat is a controller.(edytowane)
cikeZ00 - Dziś o 16:31
I feel like every emulator should have a button remapper :v
DeViL303 - Dziś o 16:31
@Kozarovv for cfw maybe is something possible with a plugin?
Borey - Dziś o 16:31
Ye, I'm REBUG rn.
Kozarovv - Dziś o 16:32
VSH is unloaded when you boot PS2, even LV2 is unloaded then. @DeViL303
Borey - Dziś o 16:32
R.I.P
DeViL303 - Dziś o 16:32
oh yeah.. :frowning:
Kozarovv - Dziś o 16:32
Ok @Borey do you tried settings in ps button menu?
Borey - Dziś o 16:32
What should I be looking for?
DeViL303 - Dziś o 16:32
anything to do with buttons :smiley:
Kozarovv - Dziś o 16:33
There is option to change analog/digital, is not directly related, but can help.
</pre>
</pre>
The mats controller lights do not work while in PS2 mode but the mat works.
===Games per Game Engine===
Same engine, same issues (mostly).
=====THPS new engine=====
*THPS4
*Underground
*Underground 2
*American Wasteland
*Project 8
*Downhill Jam
*Disney's Extreme Skate Adventure
*Guitar Hero III - Legends of Rock
*Guitar Hero - Aerosmith
*Guitar Hero - World Tour
*Guitar Hero - Metallica
*Guitar Hero 5
*Guitar Hero - Smash Hits
*Guitar Hero - Van Halen
*Band Hero
*MTX Mototrax
*Gun
===Cytology===
Emu perform check for platform ID, but there are also checks for Cytology platform (yes, netemu).
is_platform_Cyt1 found by picard seems to be first one, and second one i found at 0x111DFC seems to be is_platform_Cyt2 (?)
Is not clear that emu allow to do more when check confirm cyt platform. Maybe patch plat_info to one of know Cyt platforms?
------


===EE recompiler===
Lv2 loads the platform id from the [[Repository_Nodes|plat.id repository node]] and stores it at the Lv2 system info.<br>
Generally main r5900 recompiler subruntime is located at 0x174188 for ps2_netemu and at 0xC9C38 for gxemu. This is the place where r5900 (MIPS/COP0/COP1(FPU)/COP2(VU0-macromode)) opcodes are directed to emitter and analyzed. Jump table as is. Many opcodes jump out to different runtime due to complicated EE nature.
The [[Template:Prototype_models:DEHR|Cyt2]] platform uses the same southbridge like some [[CXD2973GB|Cok]] revisions, while [[CXD2973AGB-4|Cyt3]] uses a newer southbridge than these [[CXD2973GB|Cok]] revisions.<br>
<pre>
It's likely that the [[CXD2973AGB-4|Cyt3]] southbridge is missing the additional [[PCI]] port for the [[CXD9208GP|emulation]].<br>
jpt_1741D8: // net
The RSX on the Cyt3 platform (maybe also Cyt2) does have a video data input port ([[:File:TMU-520_1-871-645-11_A_Detail_1_(FRONT-IO).jpg|CN3101]]).
jpt_C9C7C: // gx
---------debug_stuff------------
case 0:
ee_r
ee_NOP  (real op, gxemu have flag to REALLY emit or r31,r31,r31)
ee_SPECIAL
ee_REGIMM
ee_MMI
ee_MMI0
ee_MMI1
ee_MMI2
ee_MMI3
ee_PMFHL
ee_COP0
ee_BC0
ee_C0
ee_COP1
ee_BC1
ee_S
ee_W
ee_COP2
ee_BC2
ee_VU0
ee_VU0_EX
-----------real_deal_here----------------
case 21:
ee_J
ee_JAL
ee_B
ee_BEQ
ee_BNE
ee_BEQL
ee_BNEL
ee_BLEZ
ee_BGTZ
ee_BLEZL
ee_BGTZL
ee_BLTZ
ee_BGEZ
ee_BLTZL
ee_BGEZL
ee_BLTZAL
ee_BGEZAL
ee_BLTZALL
ee_BGEZALL
ee_ADDI
ee_ADDIU
ee_LI
ee_LUI
ee_SLTI
ee_SLTIU
ee_ANDI
ee_ORI
ee_XORI
ee_DADDI
ee_DADDIU
ee_LB
ee_LBU
ee_LH
ee_LHU
ee_LW
ee_LWU
ee_LWL
ee_LWR
ee_LD
ee_LDL
ee_LDR
ee_LQ
def_1741D8
ee_PREF
ee_SB
ee_SH
ee_SW
ee_SWL
ee_SWR
ee_SD
ee_SDL
ee_SDR
ee_SQ
ee_LWC1
ee_SWC1
ee_LQC2
ee_SQC2
ee_ADD
ee_ADDU
ee_SUB
ee_SUBU
ee_SLLV
ee_SRLV
ee_SRAV
ee_DADD
ee_DADDU
ee_MOVE
ee_DSUB
ee_DSUBU
ee_DSLLV
ee_DSRLV
ee_DSRAV
ee_AND
ee_OR
ee_XOR
ee_NOR
ee_SLT
ee_SLTU
ee_SLL
ee_SRL
ee_SRA
ee_DSLL
ee_DSRL
ee_DSRA
ee_DSLL32
ee_DSRL32
ee_DSRA32
ee_MULT
ee_MULTU
ee_DIV
ee_DIVU
ee_MTHI
ee_MTLO
ee_MTSA
ee_MFHI
ee_MFLO
ee_MFSA
ee_MOVZ
ee_MOVN
ee_SYSCALL
ee_BREAK
ee_SYNC
ee_JR
ee_JALR
ee_TGE
ee_TGEU
ee_TLT
ee_TLTU
ee_TEQ
ee_TNE
ee_TGEI
ee_TGEIU
ee_TLTI
ee_TLTIU
ee_TEQI
ee_TNEI
ee_MTSAB
ee_MTSAH
ee_MADD
ee_MADDU
ee_MADD1
ee_MADDU1
ee_MULT1
ee_MULTU1
ee_DIV1
ee_DIVU1
ee_PLZCW
ee_MFHI1
ee_MTHI1
ee_MFLO1
ee_MTLO1
ee_PMFHL_LH
ee_PMFHL_LW
ee_PMFHL_SH
ee_PMFHL_SL
ee_PMFHL_UW
ee_PMTHL
ee_PSLLH
ee_PSRLH
ee_PSRAH
ee_PSLLW
ee_PSRLW
ee_PSRAW
ee_PADDW
ee_PSUBW
ee_PCGTW
ee_PMAXW
ee_PADDH
ee_PSUBH
ee_PCGTH
ee_PMAXH
ee_PADDB
ee_PSUBB
ee_PCGTB
ee_PADDSW
ee_PSUBSW
ee_PEXTLW
ee_PPACW
ee_PADDSH
ee_PSUBSH
ee_PEXTLH
ee_PPACH
ee_PADDSB
ee_PSUBSB
ee_PEXTLB
ee_PPACB
ee_PEXT5
ee_PPAC5
ee_PABSW
ee_PCEQW
ee_PMINW
ee_PADSBH
ee_PABSH
ee_PCEQH
ee_PMINH
ee_PCEQB
ee_PADDUW
ee_PSUBUW
ee_PEXTUW
ee_PADDUH
ee_PSUBUH
ee_PEXTUH
ee_PADDUB
ee_PSUBUB
ee_PEXTUB
ee_QFSRV
ee_PMADDW
ee_PSLLVW
ee_PSRLVW
ee_PMSUBW
ee_PMFHI
ee_PMFLO
ee_PINTH
ee_PMULTW
ee_PDIVW
ee_PCPYLD
ee_PMADDH
ee_PHMADH
ee_PAND
ee_PXOR
ee_PMSUBH
ee_PHMSBH
ee_PEXEH
ee_PREVH
ee_PMULTH
ee_PDIVBW
ee_PEXEW
ee_PROT3W
ee_PMADDUW
ee_PSRAVW
ee_PMTHI
ee_PMTLO
ee_PINTEH
ee_PMULTUW
ee_PDIVUW
ee_PCPYUD
ee_POR
ee_PNOR
ee_PEXCH
ee_PCPYH
ee_PEXCW
ee_MFC0
ee_MTC0
ee_BC0F
ee_BC0T
ee_BC0FL
ee_BC0TL
def_1741D8
def_1741D8
def_1741D8
def_1741D8
def_1741D8
def_1741D8
def_1741D8
ee_MFC1
ee_CFC1
ee_MTC1
ee_CTC1
ee_BC1F
ee_BC1T
ee_BC1FL
ee_BC1TL
ee_FADD
ee_FSUB
ee_FMUL
ee_FDIV
ee_FSQRT
ee_FABS
ee_FMOV
ee_FNEG
ee_FRSQRT
ee_FADDA
ee_FSUBA
ee_FMULA
ee_FMADD
ee_FMSUB
ee_FMADDA
ee_FMSUBA
ee_FCVTW
ee_FMAX
ee_FMIN
ee_FC_F
ee_FC_EQ
ee_FC_LT
ee_FC_LE
ee_FADD_A
ee_FSUB_A
ee_FCVTS
ee_QMFC2
ee_CFC2
ee_QMTC2
ee_CTC2
ee_BC2F
ee_BC2T
ee_BC2FL
ee_BC2TL
ee_VADDx
ee_VADDy
ee_VADDz
ee_VADDw
ee_VSUBx
ee_VSUBy
ee_VSUBz
ee_VSUBw
ee_VMADDx
ee_VMADDy
ee_VMADDz
ee_VMADDw
ee_VMSUBx
ee_VMSUBy
ee_VMSUBz
ee_VMSUBw
ee_VMAXx
ee_VMAXy
ee_VMAXz
ee_VMAXw
ee_VMINIx
ee_VMINIy
ee_VMINIz
ee_VMINIw
ee_VMULx
ee_VMULy
ee_VMULz
ee_VMULw
ee_VMULq
ee_VMAXi
ee_VMULi
ee_VMINIi
ee_VADDq
ee_VMADDq
ee_VADDi
ee_VMADDi
ee_VSUBq
ee_VMSUBq
ee_VSUBi
ee_VMSUBi
ee_VADD
ee_VMADD
ee_VMUL
ee_VMAX
ee_VSUB
ee_VMSUB
ee_VOPMSUB
ee_VMINI
ee_VIADD
ee_VISUB
ee_VIADDI
ee_VIAND
ee_VIOR
ee_VCALLMS
ee_VCALLMSR
ee_VADDAx
ee_VADDAy
ee_VADDAz
ee_VADDAw
ee_VSUBAx
ee_VSUBAy
ee_VSUBAz
ee_VSUBAw
ee_VMADDAx
ee_VMADDAy
ee_VMADDAz
ee_VMADDAw
ee_VMSUBAx
ee_VMSUBAy
ee_VMSUBAz
ee_VMSUBAw
ee_VITOF0
ee_VITOF4
ee_VITOF12
ee_VITOF15
ee_VFTOI0
ee_VFTOI4
ee_VFTOI12
ee_VFTOI15
ee_VMULAx
ee_VMULAy
ee_VMULAz
ee_VMULAw
ee_VMULAq
ee_VABS
ee_VMULAi
ee_VCLIP
ee_VADDAq
ee_VMADDAq
ee_VADDAi
ee_VMADDAi
ee_VSUBAq
ee_VMSUBAq
ee_VSUBAi
ee_VMSUBAi
ee_VADDA
ee_VMADDA
ee_VMULA
ee_VSUBA
ee_VMSUBA
ee_VOPMULA
ee_VNOP
ee_VMOVE
ee_VMR32
ee_VLQI
ee_VSQI
ee_VLQD
ee_VSQD
ee_VDIV
ee_VSQRT
ee_VRSQRT
ee_VWAITQ
ee_VMTIR
ee_VMFIR
ee_VILWR
ee_VISWR
ee_VRNEXT
ee_VRGET
ee_VRINIT


case 416:
-------
ee_VRXOR
</pre>


===VU0 recompiler===
Thanks for the info. Anyway this not explaining why check like this is in ps2_netemu. Which is software emulator, without any additional hardware. Maybe is just relic from ps2emu (HW emu), i try to obtain LV1 dump from DECR while emu is running, maybe this will bring some info.
[sarcasm mode ON] Due to totally lovely, and 100% sane Emotion Engine architecture [sarcasm mode OFF] VU0 run on PPC because running VU0 on SPU is not able to give needed timings/sync with EE mips core. Direct function addresses here. Few "accurate"/"inaccurate" functions are missing on that list, but you really can see pattern on other ones if needed.
<pre>
.VU0_NOP_ 0x147910
.VU0_B 0x187C48
.VU0_WAITQ 0x187C60
.VU0_Bad 0x187C64
.VU0_MOVE 0x1882A0
.VU0_LOI 0x188354
.VU0_DIV_188434          0x188434
.VU0_XITOP 0x18863C
.VU0_BAL 0x18870C
.VU0_RINIT 0x188814
.VU0_RXOR 0x1888D0
.VU0_RGET 0x1889B0
.VU0_RNEXT 0x188ABC
.VU0_IADDI 0x188D14
.VU0_ISUBIU 0x188DA8
.VU0_IADDIU 0x188E50
.VU0_IOR 0x188EF4
.VU0_ISWR 0x188F74
.VU0_ISW 0x18922C
.VU0_ILWR 0x189530
.VU0_ILW 0x1896B0
.VU0_MTIR 0x18984C
.VU0_MFIR 0x18993C
.VU0_SQRT 0x189A8C
.VU0_RSQRT 0x189D3C
.VU0_DIV 0x18A254
.VU0_SQD 0x18A670
.VU0_LQD 0x18A928
.VU0_SQI 0x18AB0C
.VU0_LQI 0x18ADB0
.VU0_SQ 0x18AF98
.VU0_LQ 0x18B24C
.VU0_MR32 0x18B424
.VU0_IAND 0x18B500
.VU0_ISUB 0x18B580
.VU0_IADD 0x18B620
.VU0_IBGEZ 0x18B6C0
.VU0_IBLEZ 0x18B778
.VU0_IBGTZ 0x18B830
.VU0_IBLTZ 0x18B8E8
.VU0_IBNE 0x18B9A0
.VU0_IBEQ 0x18BA60
.VU0_JALR 0x18BB20
.VU0_JR 0x18BBCC
.VU0_FCEQ 0x18BC3C
.VU0_NOP 0x18BDD0
.VU0_ABS 0x18BDF4
.VU0_CLIP 0x18BED0
.VU0_FTOI12 0x18C08C
.VU0_ITOF0 0x18C130
.VU0_MINIX 0x18C1D4
.VU0_MINII 0x18C348
.VU0_MINI 0x18C49C
.VU0_MAXX 0x18C5F0
.VU0_MAXI 0x18C764
.VU0_MAX 0x18C8B8
.VU0_FCGET 0x18CA0C
.VU0_FMAND 0x18CB08
.VU0_FSOR 0x18CE4C
.VU0_FSAND 0x18CF58
.VU0_FSSET 0x18D064
.VU0_FSEQ 0x18D228
.VU0_FCOR 0x18D360
.VU0_FCAND 0x18D538
.VU0_FCSET 0x18D6D8
.VU0_FTOI4 0x18D904
.VU0_FTOI0 0x18D9A8
.VU0_ITOF15 0x18DA4C
.VU0_ITOF4 0x18DAF0
.VU0_ITOF12 0x18DB94
.VU0_FTOI15 0x18DC38
.VU0_OPMSUB 0x18DCDC
.VU0_ADDZ 0x18DF0C
.VU0_SUBAX 0x18E240
.VU0_SUBAQ 0x18E570
.VU0_SUBAI 0x18E884
.VU0_SUBA 0x18EB94
.VU0_SUBY 0x18EEA4
.VU0_ADDAI 0x18F1D8
.VU0_ADDA 0x18F4EC
.VU0_MULAI 0x18F7FC
.VU0_MULA 0x18F900
.VU0_ADDI 0x18FA04
.VU0_ADD 0x18FD14
.VU0_SUB 0x190024
.VU0_OPMULA 0x190334
.VU0_ADDY 0x19047C
.VU0_ADDQ 0x1907B0
.VU0_MULI 0x190AC4
.VU0_MUL 0x190BC8
.VU0_MSUBZ 0x190CCC
.VU0_MADDY 0x19103C
.VU0_SUBQ 0x1913AC
.VU0_SUBI 0x1916BC
.VU0_MULY 0x1919CC
.VU0_MULQ 0x191AD8
.VU0_MULAZ 0x191BDC
.VU0_MULAQ 0x191CE8
.VU0_ADDAX 0x191DEC
.VU0_ADDAQ 0x192120
.VU0_MULAY 0x192434
.VU0_MULAX 0x192540
.VU0_MULAW 0x19264C
.VU0_MULW 0x192758
.VU0_MULX 0x192864
.VU0_MULZ 0x192970
.VU0_SUBAY 0x192A7C
.VU0_FMEQ 0x192DB0
.VU0_FMOR 0x19313C
.VU0_SUBAW 0x193480
.VU0_SUBAZ 0x1937B0
.VU0_ADDAW 0x193AE0
.VU0_ADDAZ 0x193E10
.VU0_MINIW 0x194140
.VU0_MINIZ 0x1942B4
.VU0_MAXW 0x194428
.VU0_MINIY 0x19459C
.VU0_MAXY 0x194710
.VU0_MAXZ 0x194884
.VU0_ADDAY 0x1949F8
.VU0_ADDX 0x194D28
.VU0_SUBW 0x195058
.VU0_SUBX 0x195388
.VU0_MSUBI 0x1956B8
.VU0_MSUB 0x195BD0
.VU0_MSUBAI 0x1960E8
.VU0_MSUBA 0x196598
.VU0_MADDI 0x196A48
.VU0_MADD 0x196F60
.VU0_MADDAI 0x197478
.VU0_MADDA 0x197928
.VU0_MSUBAX 0x197DD8
.VU0_MSUBAQ 0x198294
.VU0_MSUBY 0x198740
.VU0_MSUBQ 0x198C5C
.VU0_MADDAX 0x199178
.VU0_MADDAQ 0x199634
.VU0_MADDX 0x199AE0
.VU0_MADDQ 0x199FFC
.VU0_ADDW 0x19A518
.VU0_SUBZ 0x19A848
.VU0_MADDAZ 0x19AB78
.VU0_MSUBAY 0x19AF84
.VU0_MADDAY 0x19B394
.VU0_MADDW 0x19B7A4
.VU0_MSUBW 0x19BBB4
.VU0_MADDAW 0x19BFC4
.VU0_MSUBAW 0x19C47C
.VU0_MADDZ 0x19C934
.VU0_MSUBX 0x19CD44
.VU0_MSUBAZ 0x19D154
Accurate.VU0_ADD__all__VU0 0x19D610
Accurate.VU0_SUB__all__VU0 0x19D858
Accurate.VU0_MADDY_VU0 0x19E26C
Accurate.VU0_MSUBZ_VU0 0x19E37C
.VU0_MADDbc_inaccurate 0x19E628
</pre>


===Accurate math===
===Shaders===
Accurate add/sub for COP1(FPU)/COP2(VU0 macromode)/VU0 is located at 0x1871A0<br>
Editable!  
Accurate mul/div for COP1(FPU) ONLY! is located at 187B60<br>


===get reg===
Shaders are located on 0x761000 to 0x76551F in file. There are two kind of file headers 00001B5B, and 00001B5C.  
After resolving above functions, you can see some sub_ in recompiler runtimes. This are usually used to translate ppc/spu reg to mips/c0/c1/c2/vu0/vu1 regs. Easy to cache due to extrdi which indicate field/reg bytes.


== List of unused functions in ps2_netemu ==
*FontShader - vpshader_bin_0 (vertex program)/ fpshader_bin_0 (fragment program)
*ImageShader - vpshader_bin_1 (vertex program) / fpshader_bin_1 (fragment program) - Diff settings for upscaler, or without it. (off_8211E0 and off_8214B0 in memory)
*Gauss - vpshader_bin_2 (vertex program) / fpshader_bin_2 (fragment program)


Unused Emotion Engine opcodes from that list are inlined into different function. But somehow, they ended up here also as separate totally unused functions. Giving us a lot of space for custom stuff if needed, this can be safely owerwritten by our own code.  
Decompiler & info: https://github.com/RPCS3/rpcs3/tree/master/rpcs3/Emu/RSX/Common


Name                      Address      Size
===gxemu/netemu 0x01===
                  configs
Weird memory offset: https://github.com/Zarh/Get_CONFIG/blob/7aab2cedf28564af8351220689940cfb780eea98/log.txt#L10350
SLUS_204.71_0x0E          0x170CCC 0x68
<br/>EE memory end at 1FFFFFFF
unused_config_cmd_0x10_  0x1489A4 0x58
unused_config_cmd_0x10    0x1489FC 0x58
unused_config_cmd_0x0E_  0x148A54 0x4C
unused_config_cmd_0x0E    0x148AA0 0x4C
                  recompiler
unused_ee_MFSA            0x148F60 0x8C
unused_ee_ORI            0x148FEC 0xC4
unused_ee_MTLO            0x1490B0 0x80
unused_ee_MTHI            0x149130 0x80
unused_ee_LUI            0x1493D0 0x90
unused_ee_TNE            0x149AFC 0xA8
unused_ee_TLT            0x149BA4 0xAC
unused_ee_TGE            0x149C50 0xAC
unused_ee_TEQ            0x149CFC 0xAC
unused_ee_BC1TL          0x14A448 0x78
unused_ee_BC1FL          0x14A4C0 0x74
unused_ee_BC1T            0x14A534 0x78
unused_ee_BC1F            0x14A5AC 0x74
unused_ee_MTSA            0x14AC7C 0x88
unused_ee_VIADDI          0x14AD04 0x94
unused_ee_VIADD          0x14AD98 0xA8
unused_ee_VIOR            0x14AE40 0xA8
unused_ee_MFLO            0x14AFE0 0x98
unused_ee_MFHI            0x14B078 0x98
unused_ee_BC2TL          0x14B850 0xC0
unused_ee_BC2FL          0x14B910 0xBC
unused_ee_BC2T            0x14B9CC 0xC0
unused_ee_BC2F            0x14BA8C 0xBC
unused_ee_BC0TL          0x14BB48 0xC0
unused_ee_BC0FL          0x14BC08 0xBC
unused_ee_BC0T            0x14BCC4 0xC0
unused_ee_BC0F            0x14BD84 0xBC
unused_ee_VIAND          0x14BF64 0xA8
unused_ee_DSRA32          0x14E09C 0xC8
unused_ee_DSRA            0x14E164 0xC4
unused_ee_FABS            0x14E808 0x8C
unused_ee_PAND            0x14E894 0xB8
unused_ee_PSUBW          0x14E94C 0xB8
unused_ee_PCEQW          0x14EA04 0xB8
unused_ee_PADDW          0x14EABC 0xB8
unused_ee_FMADDA          0x14EC3C 0xA4
unused_ee_FMADD          0x14ECE0 0xAC
unused_ee_FADDA          0x14EE54 0xA0
unused_ee_FADD            0x14EEF4 0xA8
unused_ee_FNEG            0x14EF9C 0x8C
unused_ee_PXOR            0x14F028 0xB8
unused_ee_PNOR            0x15035C 0xB8
unused_ee_QMTC2          0x15096C 0x8C
unused_ee_QMFC2          0x1509F8 0x98
unused_ee_FMOV            0x150A90 0x8C
unused_ee_POR            0x150B1C 0xB8
unused_ee_PMTLO          0x150BD4 0x80
unused_ee_PMTHI          0x150C54 0x80
unused_ee_PMFLO          0x150CD4 0x98
unused_ee_PMFHI          0x150D6C 0x98
unused_ee_FSUBA          0x15268C 0xA0
unused_ee_FSUB            0x15272C 0xA8
unused_ee_PROT3W          0x152E48 0xB4
unused_ee_PREVH          0x152EFC 0xB4
unused_ee_PEXEW          0x153644 0xB4
unused_ee_PEXEH          0x1536F8 0xB4
unused_ee_PEXCW          0x1537AC 0xB4
unused_ee_PEXCH          0x153860 0xB4
unused_ee_PCGTW          0x155210 0xB8
unused_ee_VISUB          0x1564B8 0xA8
unused_ee_FCVTW          0x156930 0x8C
unused_ee_PSUBUW          0x1578B4 0xB8
unused_ee_FC_F            0x157AD4 0x54
unused_ee_PSUBSW          0x157E4C 0xB8
unused_ee_PSUBSH          0x157F04 0xB8
unused_ee_PSUBSB          0x157FBC 0xB8
unused_ee_PSUBH          0x158074 0xB8
unused_ee_PSUBB          0x15812C 0xB8
unused_ee_MTLO1          0x158480 0x80
unused_ee_MTHI1          0x158500 0x80
unused_ee_MFLO1          0x158580 0x98
unused_ee_MFHI1          0x158618 0x98
unused_ee_SRA            0x15B4D0 0xA4
unused_ee_PMAXW          0x15B958 0xB8
unused_ee_PMAXH          0x15BAF8 0xB8
unused_ee_PEXTUW          0x15C228 0xB8
unused_ee_PEXTUH          0x15C2E0 0xB8
unused_ee_PEXTUB          0x15C398 0xB8
unused_ee_PEXTLW          0x15C450 0xB8
unused_ee_PEXTLH          0x15C508 0xB8
unused_ee_PCGTH          0x15D664 0xB8
unused_ee_PCGTB          0x15D71C 0xB8
unused_ee_PCEQH          0x15D7D4 0xB8
unused_ee_PCEQB          0x15D88C 0xB8
unused_ee_PADDH          0x15DA5C 0xB8
unused_ee_PADDUW          0x15DB14 0xB8
unused_ee_PADDUH          0x15DBCC 0xB8
unused_ee_PADDUB          0x15DC84 0xB8
unused_ee_PADDSW          0x15DD3C 0xB8
unused_ee_PADDSH          0x15DDF4 0xB8
unused_ee_PADDSB          0x15DEAC 0xB8
unused_ee_PADDB          0x15DF64 0xB8
unused_ee_MTSAH          0x15E01C 0xB4
unused_ee_MTSAB          0x15E0D0 0xB4
unused_ee_XORI            0x15E184 0xC4
unused_ee_TNEI            0x15E248 0x8C
unused_ee_TLTI            0x15E2D4 0x90
unused_ee_TGEI            0x15E364 0x90
unused_ee_TEQI            0x15E3F4 0x90
unused_ee_BLTZ_notsure    0x15E484 0x8C
unused_ee_BLTZAL_notsure  0x15E510 0xA4
unused_ee_BLTZALL_notsure 0x15E5B4 0xA0
unused_ee_TLTU            0x15EB5C 0xAC
unused_ee_TGEU            0x15EC08 0xAC
unused_ee_TLTIU          0x15ECB4 0x90
unused_ee_TGEIU          0x15ED44 0x90
unused_ee_SRL            0x15F624 0xA4
unused_ee_SLL            0x15FB70 0xC8
unused_ee_JALR            0x160BE0 0xDC
unused_ee_DSRL32          0x160CBC 0xC8
unused_ee_DSRL            0x160D84 0xC4
unused_ee_DSLL32          0x160F7C 0xC8
unused_ee_DSLL            0x161044 0xC4
unused_ee_ADDI_UNK        0x16FED0 0x7C
unused_ee_unk_NOP        0x16FF4C 0x1C
unused_ee_unk_NOP_        0x16FF68 0x1C
unused_ee_ADDI_UNK1      0x16FF84 0x6C
unused_ee_unk_NOP__      0x16FFF0 0x1C
unused_ee_ADDI_UNK2      0x17000C 0x6C
unused_ee_JR              0x170C1C 0xB0


== Softemu questions ==
* Epic, this looks like PS1 game config in PS2 emu. Still ID mismatch, but mapping seems to be valid for PSX :D


Hi,
===12===


You are clearly the one familiar with ps2 emus on ps3. I'm researching stuff about softemu, and I wanted to try and run some games on it. There used to be a list of the games that ran on tortuga-cave site ( can be accessed through wayback archive). Anyways, I also noticed the only emulator that was tested was version 2.6 ? But softemu was however still released up to FW 4.01. Did nobody test the latest revision of it? I was trying to record some gameplays because it's a fun topic and nobody has really recorded gameplays from it directly. But I can't for the love of god get any games to work. I tried on a slim and now on CECHL. I only have a couple of official disc games, and I tried to run them from FSM mode. PS2 discs are recognised but go to black screen. I suppose my games were not supported all that well. So I was wondering could you make some type of emulator-switcher tool that would simply allow us to switch back to softemu on latest firmwares? Something that would work on evilnat perhaps?
03 = EE
* I think testing on tortuga was done on 3.41 emulator (they used cobra dongle which i think was first available somewhere around 3.55 fw). I'm not familiar with FSM method, i read about it on wiki, but never heard about it working anywhere else. Your best bet will be downgrade to firmware like 3.55 and try there. Getting softemu to run on newer firmware require more work. Simple fact that softemu is old enough to use different keyset makes it impossible to just switch emus. Sadly, i can't help with getting it to run. I only know emulator side of things, firmware patches required to get it to work is not something i can do by myself. I know you want to do this for fun, but softemu had broken HW shaders and its compatibility was rather pure due to few different factors. Broken HW shaders mean visual glitches in many titles. Rushed development resulted in mostly copy pasted SPU code from gxemu, which was later heavily changed for netemu (dedicated software renderer on SPU, abandon of magic gate which allowed to use one more SPE core for emu, etc.). Like i said above your best bet is downgrade to 3.55 and trying there. Maybe searching for Cobra dongle with firmware for 3.55 too, but they will be probably highly overpriced now due to collectible value. --[[User:Kozarovv|Kozarovv]] ([[User talk:Kozarovv|talk]]) 22:31, 7 August 2024 (CEST)
02 = vu/cop2?


== PSPEmu ==


Well I have tested the version you shared with your friend mrjaredbeta. The one taken from fw 4.01. And it's great, but cannot recognise memory cards. So I finally got the cobra dongle, and turns out that one is able to recognise memory cards and save games.  But cobra dongle thing only works with its own firmware sadly. I tried to replace the softemu file with 4.01 , the one you patched and also ofw one, but it would not boot any games with those. So now I am wondering, could it be possible to patch softemu 4.01 so that would also work with cobra dongle? I can send you the one that cobra uses , maybe you can take a look. I know the emulator is glitched and all, but I have a strange obsession with it lol.
The key for minis2 is known, you can just use npdtool to encrypt it. ofc you can patch it to read unencrypted ones but whats the advantage?
* Getting new emu to work with cobra is not easy. Getting all hooks ported, etc. I have no plan to do that. Cobra version recognizes memory cards because cobra launches emulator with prepared ps2bootparam. Probably patch to handle one memory card with hardcoded name can be done to make it work on new emu, not sure. I don't think there is anything i can do to help you with any of that.--[[User:Kozarovv|Kozarovv]] ([[User talk:Kozarovv|talk]]) 09:10, 11 September 2024 (CEST)


Another question related to how ps2 upscaler works on CECHA consoles. So when the ps2 upscaler setting is on, some PAL PS2 games load into black screen on CECHAs. So I was wondering if anybody has researched how that upscaler functions or why it prevents PAL games to boot correctly? Is it something that can be potentially fixed? Do you know if this problem is present on DECHA consoles ?
are you interested in any specific game?  
* I never heard about issue like that. It's probably TV that don't like mix of 50Hz and some resolutions. I know someone who have CECH A and DECH A, everything works fine for him regardless of applied settings and game region, but he lives in EU, so TV is 50/60Hz ready for whole range of screen resolutions. I know that some 60Hz TVs don't like 576i input in PSX games on PS3 too. --[[User:Kozarovv|Kozarovv]] ([[User talk:Kozarovv|talk]]) 20:03, 27 September 2024 (CEST)


It is actually a known issue (well, known to people who have tried it). I have several PAL-games that will not boot on CECHAs unless upscaler is turned off. Call of Duty Finest hour and Death by Degrees are two examples of that. I also live in EU and my TV does support both 50 and 60hz too. Hmm, not sure about specific resolutions though. It also could be that your friend got lucky and never tried those specific games. I don't have a DECHA to test it out though, maybe he could try to test the games I mentioned?
https://github.com/hrydgard/ppsspp/commits/525cce095a6e4ac569736c14dbcde7b64a92328f/assets/compat.ini
* My friend tested that on his PS3 and indeed Death by Degrees is throwing no signal after memory card check when upscaler is active (btw. it's important to know when exactly issue occur, this helps people without CECHA look into it). I don't know how this is known issue when people that can potentially fix it are not aware of it. :) Anyway. You may want to create thread on psx-place or other place with active Cobra/CFW developers to let them know that issue exist. Info which games fail at which point will be help too. Without that there is slim chance to fix it. --[[User:Kozarovv|Kozarovv]] ([[User talk:Kozarovv|talk]]) 09:33, 30 September 2024 (CEST)


I suppose you are correct, I wrongly assumed it is a known issue. But maybe it is not. Devs seem to often ignore CECHA models, they focus on slims and the later ones. But I can post a message, yeah. Btw, I have seen your latest progress on gx-emu, and I was also wondering if you can check if it is realistically possible to add GSM options to ps2-emu (on CECHAs) ? Because GSM is a tool that can force ps2 games into different video modes, like 1080i. And since it works on CECHAs as well (through OPL), perhaps it could be integrated somehow into the emulator to simply switch resolutions when opening the settings? I am talking about this tool https://www.ps2-home.com/forum/viewtopic.php?f=12&t=53
i patched some games and found some more configurations:  
* GSM operates by intercepting communications between EE and GS to set required registers. There is no way to do that on ps2_emu, since EE+GS is not exposing this communication outside of chip.


== Syscon Thermal Zones ==
http://www.psdevwiki.com/ps3/Talk:PSP_Emulation#PSP_compatibility_lists


*0x00: 1st BE Primary
--[[User:Mysis|Mysis]]
*0x01: RSX Primary
*0x02: XDR Primary
*0x03: BE VR
*0x04: RSX VR
*0x05: GDDR3 VR
*0x06: XDR VR
*0x07: AC/DC
*0x08: BD Primary
*0x09: BD Secondary
*0x0A: Air Intake
*0x0B: inside chasis
*0x0C: XIO trace
*0x0D: IOIF0 trace
*0x0E: IOIF1 trace
*0x0F: GbE
*0x10: USB
*0x11: misc
*0x12: 1st HDD
*0x13: 2nd HDD
*0x14: SB
*0x15: EE+GS


Most of that is unavailable even in late Cytology...
* My point is to use PSP Remaster Launcher because it allow to use minis2 config directly with decrypted ISO. With this patch I should be able to run test games very easy/fast, because I can use plain ISO + plain minis2.txt without need for external tools. I can then even edit config thru ftp text editor without need to do any additional steps (specially useful with black screen games). Is not necessary, just make things much easier. I'm interested in overall tests with games I have, not any specific game. --[[User:Kozarovv|Kozarovv]]


== fsck on ps3 ==
> Ok, patching is quite easy, its in the psp_emulator.self there is only one sceNpDrmIsAvailable followed by a OpenFile...:
<syntaxhighlight lang="asm">
seg001:000000000001158C 41 9E 00 1C                beq      cr7, no_minis2
seg001:0000000000011590 7B A3 00 20                clrldi    r3, r29, 32
seg001:0000000000011594 7F E4 FB 78                mr        r4, r31
seg001:0000000000011598 48 04 98 DD                bl        _sceNp_sceNpDrmIsAvailable -> 38 60 00 00                li        r3, 0
seg001:000000000001159C E8 41 00 28                ld        r2, 0x18A0+var_1878(r1)
seg001:00000000000115A0 2F 83 00 00                cmpwi    cr7, r3, 0
seg001:00000000000115A4 41 9E 06 58                beq      cr7, loc_11BFC
seg001:00000000000115A8
seg001:00000000000115A8            no_minis2:                              # CODE XREF: main+74C�j
seg001:00000000000115A8                                                    # main+DE4�j ...
seg001:00000000000115A8 80 1E 00 08                lwz      r0, 8(r30)
seg001:00000000000115AC 2F 80 00 02                cmpwi    cr7, r0, 2
seg001:00000000000115B0 41 9E 05 54                beq      cr7, read_2nd_settings


Write to 0x10520 raw HDD offset (using ps3 "simple fs"). This match UFS2 superblock offset 0x520, which is "fs_flags". Write old value ored with 4. Value 4 means FS_NEEDSFSCK. All this is quite standard UFS2 behavior.
and possibly, but not sure:
seg001:0000000000011BFC            loc_11BFC:                              # CODE XREF: main+764�j
seg001:0000000000011BFC 38 00 00 02                li        r0, 2
seg001:0000000000011C00 7F E3 FB 78                mr        r3, r31
seg001:0000000000011C04 38 80 00 00                li        r4, 0
seg001:0000000000011C08 38 A1 00 74                addi      r5, r1, 0x18A0+var_182C
seg001:0000000000011C0C 38 C1 00 90                addi      r6, r1, 0x18A0+var_1810 -> 38 C0 00 00                li        r6, 0
seg001:0000000000011C10 38 E0 00 08                li        r7, 8                  -> 38 E0 00 00                li        r7, 0
seg001:0000000000011C14 F8 01 00 90                std      r0, 0x18A0+var_1810(r1)
seg001:0000000000011C18 48 04 91 DD                bl        _sys_fs_cellFsOpen
</syntaxhighlight>
but if you are using cobra mode then cobra is checking psp_emulator hash? and might not apply the other patches: https://github.com/Joonie86/COBRA-7.3/blob/master/481/REX/SRC/stage2/modulespatch.h ? Not sure how it works...


== Temp - Waiting for release ==


{{BoxcommGX|id=0x2C|net_id=0x0A|data=FIXME|}}
[[User:Mysis|Mysis]]
Patch 32 bit opcodes of EE executable code. '''Warning! This is custom command and it is not available in not patched emulator!'''
Format:
32 bit ID  | 32 bit align | 64bit ptr to emu memory | 32 bit count | 32 bit align
0x0000002C |  0x00000000  |  0x0000000000341190    |  0x00000002  | 0x00000000


Additional example data at 0x341190 looks like this:
  32 bit EE offset  | 32 bit align | 32 bit original opcode | 32 bit align | 32 bit replace opcode | 32 bit align 
    0x00122780    |  0x00000000  |      0x27BDFE10      |  0x00000000  |      0x27BDFD00      |  0x00000000
   
   
due to patch count == 2 in this example, there is next set of data right after first one:
* Cobra hash is no problem, I can recompile stage2, or just even edit hash in binary after adding patch. Thanks for sharing, you just made my testing much easier!
  32 bit EE offset  | 32 bit align | 32 bit original opcode | 32 bit align | 32 bit replace opcode | 32 bit align 
    0x00122AE8    |  0x00000000  |      0x27BD01F0      |  0x00000000  |      0x27BD0300      |  0x00000000


<div class="mw-collapsible mw-collapsed" data-expandtext="{{int:Show}}" data-collapsetext="{{int:Hide}}" style="width:1000px; background:#cccccc;">'''More info'''
--[[User:Kozarovv|Kozarovv]]
<div class="mw-collapsible-content" style="text-align:left;">
This command read and write opcodes as a 32 bit value. Command implementation helps with netemu 0x0A ports.
Example ps2_netemu 0x0A config translation.
<br>Original config.
3D 00 00 00 57 44 00 00 <-- not relevant.
0A 00 00 00 02 00 00 00 <-- CMD 0x0A, count 0x02
80 27 12 00 10 FE BD 27 00 FD BD 27 <-- addr, org opcode, replace opcode
E8 2A 12 00 F0 01 BD 27 00 03 BD 27 <-- addr, org opcode, replace opcode
Gx config.
00 00 00 84 79 85 29 05 00 34 11 78 00 00 00 01 <-- single command in this example, count is elsewhere
00 00 00 2C 00 00 00 00 00 00 00 00 00 34 11 90 00 00 00 02 00 00 00 00 <-- CMD 0x2C, ptr to command data, count 0x02.
00 12 27 80 00 00 00 00 27 BD FE 10 00 00 00 00 27 BD FD 00 00 00 00 00 <-- addr, org opcode, replace opcode
00 12 2A E8 00 00 00 00 27 BD 01 F0 00 00 00 00 27 BD 03 00 00 00 00 00 <-- addr, org opcode, replace opcode
Single line explanation, gx command is big endian, netemu is little endian:
    00 12 27 80    | 00 00 00 00 |  27 BD FE 10  | 00 00 00 00 |  27 BD FD 00  | 00 00 00 00
ee addr from 0x0A |    align    | original opcode |    align    | replace opcode |   align
</div>
</div>
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