Editing Template:Syscon pinout BGA 200 pads
Jump to navigation
Jump to search
The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then publish the changes below to finish undoing the edit.
Latest revision | Your text | ||
Line 6: | Line 6: | ||
<div style="overflow:auto; <includeonly>height:800px;</includeonly>"> | <div style="overflow:auto; <includeonly>height:800px;</includeonly>"> | ||
{|class="wikitable sortable" style="width:100%; line-height: | {|class="wikitable sortable" style="width:100%; line-height:120%; font-size:90%" | ||
|+ {{captionlinks|Syscon pinout BGA 200 pads}} | |+ {{captionlinks|Syscon pinout BGA 200 pads}} | ||
|- | |- | ||
Line 45: | Line 45: | ||
| data-sort-value="A99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" | | | data-sort-value="A99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" | | ||
|- | |- | ||
| data-sort-value="B01" | B1 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || | | data-sort-value="B01" | B1 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || AVREF1 || {{pini}} || data-sort-value="ZV33" style="color:#888" | +3.3V_EVER | ||
|- | |- | ||
| data-sort-value="B02" | B2 || J || DISC_OUT8_SW || ? || Connected to BluRay Drive connector (CN3221) pin 57 | | data-sort-value="B02" | B2 || J || DISC_OUT8_SW || ? || Connected to BluRay Drive connector (CN3221) pin 57 | ||
Line 71: | Line 71: | ||
| data-sort-value="B13" | B13 || E || SB_EBUS_BRDY || ? || SS2_BRDY (StarShip2 related) | | data-sort-value="B13" | B13 || E || SB_EBUS_BRDY || ? || SS2_BRDY (StarShip2 related) | ||
|- | |- | ||
| data-sort-value="B14" | B14 || E || VD_CECI1 || | | data-sort-value="B14" | B14 || E || VD_CECI1 || ? || | ||
|- | |- | ||
| data-sort-value="B15" | B15 || E || POW_FAIL || ? || Connected to [[Components#Mitsumi_PST3642UL_.28IC_for_CMOS_System_Reset.29|Mitsumi PST3642UL]] (IC6023) pin 4. Used to monitor the state of +12V_MAIN power rail | | data-sort-value="B15" | B15 || E || POW_FAIL || ? || Connected to [[Components#Mitsumi_PST3642UL_.28IC_for_CMOS_System_Reset.29|Mitsumi PST3642UL]] (IC6023) pin 4. Used to monitor the state of +12V_MAIN power rail | ||
Line 115: | Line 115: | ||
| data-sort-value="D01" | D1 || O || MK_I2C_SCL || ? || Connected to [[Timebases#ICS_ICS1493G-18LFT|ICS1493G-18LFT]] clock generator (IC5001) pin 46 | | data-sort-value="D01" | D1 || O || MK_I2C_SCL || ? || Connected to [[Timebases#ICS_ICS1493G-18LFT|ICS1493G-18LFT]] clock generator (IC5001) pin 46 | ||
|- | |- | ||
| data-sort-value="D02" | D2 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || | | data-sort-value="D02" | D2 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || VDD2 || {{pini}} || data-sort-value="ZV15" style="color:#888" | +1.5V_RSX_VDDIO | ||
|- | |- | ||
| data-sort-value="D03" | D3 || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" style="color:#888" | Missing pad | | data-sort-value="D03" | D3 || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" style="color:#888" | Missing pad | ||
|- | |- | ||
| data-sort-value="D04" | D4 || O || XDR_FET_RST || | | data-sort-value="D04" | D4 || O || XDR_FET_RST || ? || XDR_RQ_RST | ||
|- | |- | ||
| data-sort-value="D05" | D5 || O || XCG_EN || ? || Connected to [[Timebases#ICS_ICS9218AGLFT_.28IC_CLOCK_GEN_RAMBUS_XDR_28-TSSOP.29|ICS9218AGLFT]] (IC5002) pin 11 (switches BE_Y0_RQ_CTM/N, BE_Y1_RQ_CTM/N)<br>Connected to [[Timebases#ICS_ICS9218AGLFT_.28IC_CLOCK_GEN_RAMBUS_XDR_28-TSSOP.29|ICS9218AGLFT]] (IC5003) pin 11 (switches BE_PLL_REFCLK_P/N)<br>Connected to [[Timebases#ICS_ICS9214DGLFT_.28IC_CLOCK_GEN_RAMBUS_XDR_28-TSSOP.29|ICS9214DGLFT]] (IC5004) pin 11 (switches BE_RC_REFCLK_P/N, RSX_RC_REFCLK_P/N, SB_RC_REFCLK_P/N) | | data-sort-value="D05" | D5 || O || XCG_EN || ? || Connected to [[Timebases#ICS_ICS9218AGLFT_.28IC_CLOCK_GEN_RAMBUS_XDR_28-TSSOP.29|ICS9218AGLFT]] (IC5002) pin 11 (switches BE_Y0_RQ_CTM/N, BE_Y1_RQ_CTM/N)<br>Connected to [[Timebases#ICS_ICS9218AGLFT_.28IC_CLOCK_GEN_RAMBUS_XDR_28-TSSOP.29|ICS9218AGLFT]] (IC5003) pin 11 (switches BE_PLL_REFCLK_P/N)<br>Connected to [[Timebases#ICS_ICS9214DGLFT_.28IC_CLOCK_GEN_RAMBUS_XDR_28-TSSOP.29|ICS9214DGLFT]] (IC5004) pin 11 (switches BE_RC_REFCLK_P/N, RSX_RC_REFCLK_P/N, SB_RC_REFCLK_P/N) | ||
|- | |- | ||
| data-sort-value="D06" | D6 || H || VD_CECI0 || | | data-sort-value="D06" | D6 || H || VD_CECI0 || ? || | ||
|- | |- | ||
| data-sort-value="D07" | D7 || H || RSX_POW_FAIL<!--RS_POW_FAIL is an official typo, the name appears several times but only one of them have the typo--> || {{pini}} || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6201) pin 7 | | data-sort-value="D07" | D7 || H || RSX_POW_FAIL<!--RS_POW_FAIL is an official typo, the name appears several times but only one of them have the typo--> || {{pini}} || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6201) pin 7 | ||
Line 157: | Line 157: | ||
| data-sort-value="E05" | E5 || O || PO0 || {{pinnc}} || data-sort-value="ZNC" style="color:#888" | Not Connected (CL4086) | | data-sort-value="E05" | E5 || O || PO0 || {{pinnc}} || data-sort-value="ZNC" style="color:#888" | Not Connected (CL4086) | ||
|- | |- | ||
| data-sort-value="E06" | E6 || H || HDMI_INT || | | data-sort-value="E06" | E6 || H || HDMI_INT || ? || Connected to [[TC7WP3125FK]] (IC2501) pin 6. This is a syscon input at 3.3V<br> The [[TC7WP3125FK]] converts the signal originally triggered by [[Sil9132CBU]] pad E10 ? at 1.5V and converts it to 3.3V for syscon<br>The [[TC7WP3125FK]] also converts the signal RS_SPDO0 (at 1.5V) into RS_SPDO0_33 (at 3.3V) | ||
|- | |- | ||
| data-sort-value="E07" | E7 || H || MECHA_INT || ? || Not connected in retail PS3 models (testpad CL4102). The related SouthBridge pad is tied to GND with a 10k resistor (R3163) | | data-sort-value="E07" | E7 || H || MECHA_INT || ? || Not connected in retail PS3 models (testpad CL4102). The related SouthBridge pad is tied to GND with a 10k resistor (R3163) | ||
Line 169: | Line 169: | ||
| data-sort-value="E11" | E11 || F || SB_CGRESET || ? || SB_CGRST (the name indicates that it resets the clock generator for the southbridge) | | data-sort-value="E11" | E11 || F || SB_CGRESET || ? || SB_CGRST (the name indicates that it resets the clock generator for the southbridge) | ||
|- | |- | ||
| data-sort-value="E12" | E12 || F || BT_WAKEON || | | data-sort-value="E12" | E12 || F || BT_WAKEON || ? || Connected to wifi board connector (CN3701) pin 30 (named BT_WAKE). This is a syscon input | ||
|- | |- | ||
| data-sort-value="E13" | E13 || F || PF1<br>BE_VCS_1.30_ON || ? || [[COK-001]]/[[COK-002]] PF1 (Not connected)<br>[[SEM-001]] BE_VCS_1.30_ON | | data-sort-value="E13" | E13 || F || PF1<br>BE_VCS_1.30_ON || ? || [[COK-001]]/[[COK-002]] PF1 (Not connected)<br>[[SEM-001]] BE_VCS_1.30_ON | ||
Line 191: | Line 191: | ||
| data-sort-value="F05" | F5 || O || DISC_IN_MECHA || ? || Connected to BluRay Drive connector (CN3221) pin 55 | | data-sort-value="F05" | F5 || O || DISC_IN_MECHA || ? || Connected to BluRay Drive connector (CN3221) pin 55 | ||
|- | |- | ||
| data-sort-value="F06" | F6 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || | | data-sort-value="F06" | F6 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || VDD3 || {{pini}} || data-sort-value="ZV33" style="color:#888" | +3.3V_EVER | ||
|- | |- | ||
| data-sort-value="F07" | F7 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || | | data-sort-value="F07" | F7 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || AVDD || {{pini}} || data-sort-value="ZV33" style="color:#888" | +3.3V_EVER | ||
|- | |- | ||
| data-sort-value="F08" | F8 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || | | data-sort-value="F08" | F8 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || VDD3 || {{pini}} || data-sort-value="ZV33" style="color:#888" | +3.3V_EVER | ||
|- | |- | ||
| data-sort-value="F09" | F9 || data-sort-value="ZNC" | || data-sort-value="ZNC" | || {{pinnc}} || data-sort-value="ZNC" style="color:#888" | Not Connected | | data-sort-value="F09" | F9 || data-sort-value="ZNC" | || data-sort-value="ZNC" | || {{pinnc}} || data-sort-value="ZNC" style="color:#888" | Not Connected | ||
|- | |- | ||
| data-sort-value="F10" | F10 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || | | data-sort-value="F10" | F10 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || VDD3 || {{pini}} || data-sort-value="ZV33" style="color:#888" | +3.3V_EVER | ||
|- | |- | ||
| data-sort-value="F11" | F11 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || | | data-sort-value="F11" | F11 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || VDDbat || ? || +battery | ||
|- | |- | ||
| data-sort-value="F12" | F12 || D || MK_EN || ? || Connected to [[Timebases#ICS_ICS1493G-18LFT|ICS1493G-18LFT]] clock generator (IC5001) pin 16 | | data-sort-value="F12" | F12 || D || MK_EN || ? || Connected to [[Timebases#ICS_ICS1493G-18LFT|ICS1493G-18LFT]] clock generator (IC5001) pin 16 | ||
Line 235: | Line 235: | ||
| data-sort-value="G10" | G10 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || {{cellcolors|#333|#fff}} VSS || {{pini}} || data-sort-value="ZG" style="color:#888" | Ground | | data-sort-value="G10" | G10 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || {{cellcolors|#333|#fff}} VSS || {{pini}} || data-sort-value="ZG" style="color:#888" | Ground | ||
|- | |- | ||
| data-sort-value="G11" | G11 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || | | data-sort-value="G11" | G11 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || VDDep || {{pini}} || data-sort-value="ZV33" style="color:#888" | +3.3V_EVER | ||
|- | |- | ||
| data-sort-value="G12" | G12 || D || BEVRM_VID4 || ? || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6103) pin 3 | | data-sort-value="G12" | G12 || D || BEVRM_VID4 || ? || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6103) pin 3 | ||
Line 261: | Line 261: | ||
| data-sort-value="H06" | H6 || L || PL0 || {{pinnc}} || data-sort-value="ZNC" style="color:#888" | Not Connected | | data-sort-value="H06" | H6 || L || PL0 || {{pinnc}} || data-sort-value="ZNC" style="color:#888" | Not Connected | ||
|- | |- | ||
| data-sort-value="H07" | H7 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || | | data-sort-value="H07" | H7 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || DVDD || {{pini}} || data-sort-value="ZV18" style="color:#888" | +1.8V_EVER | ||
|- | |- | ||
| data-sort-value="H08" | H08 || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" style="color:#888" | Missing pad | | data-sort-value="H08" | H08 || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" style="color:#888" | Missing pad | ||
Line 267: | Line 267: | ||
| data-sort-value="H09" | H09 || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" style="color:#888" | Missing pad | | data-sort-value="H09" | H09 || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" style="color:#888" | Missing pad | ||
|- | |- | ||
| data-sort-value="H10" | H10 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || | | data-sort-value="H10" | H10 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || VDD3 || {{pini}} || data-sort-value="ZV33" style="color:#888" | +3.3V_EVER | ||
|- | |- | ||
| data-sort-value="H11" | H11 || data-sort-value="ZC" | <abbr title="Reset & Clock">CLK</abbr> || TESTMODE || | | data-sort-value="H11" | H11 || data-sort-value="ZC" | <abbr title="Reset & Clock">CLK</abbr> || TESTMODE || ? || | ||
|- | |- | ||
| data-sort-value="H12" | H12 || D || BEVRM_VID2 || ? || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6103) pin 1 | | data-sort-value="H12" | H12 || D || BEVRM_VID2 || ? || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6103) pin 1 | ||
Line 293: | Line 293: | ||
| data-sort-value="J05" | J5 || L || PL3 || {{pinnc}} || data-sort-value="ZNC" style="color:#888" | Not Connected | | data-sort-value="J05" | J5 || L || PL3 || {{pinnc}} || data-sort-value="ZNC" style="color:#888" | Not Connected | ||
|- | |- | ||
| data-sort-value="J06" | J6 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || | | data-sort-value="J06" | J6 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || VDD3 || {{pini}} || data-sort-value="ZV33" style="color:#888" | +3.3V_EVER | ||
|- | |- | ||
| data-sort-value="J07" | J7 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || | | data-sort-value="J07" | J7 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || DVDD || {{pini}} || data-sort-value="ZV18" style="color:#888" | +1.8V_EVER | ||
|- | |- | ||
| data-sort-value="J08" | J08 || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" style="color:#888" | Missing pad | | data-sort-value="J08" | J08 || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" style="color:#888" | Missing pad | ||
Line 301: | Line 301: | ||
| data-sort-value="J09" | J09 || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" style="color:#888" | Missing pad | | data-sort-value="J09" | J09 || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" style="color:#888" | Missing pad | ||
|- | |- | ||
| data-sort-value="J10" | J10 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || | | data-sort-value="J10" | J10 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || DVDD || {{pini}} || data-sort-value="ZV18" style="color:#888" | +1.8V_EVER | ||
|- | |- | ||
| data-sort-value="J11" | J11 || data-sort-value="ZC" | <abbr title="Reset & Clock">CLK</abbr> || RST || ? || Connected to [[Service_Connectors#CN4009| service connector]] (CN4009) pin 8 | | data-sort-value="J11" | J11 || data-sort-value="ZC" | <abbr title="Reset & Clock">CLK</abbr> || RST || ? || Connected to [[Service_Connectors#CN4009| service connector]] (CN4009) pin 8 | ||
Line 317: | Line 317: | ||
| data-sort-value="J99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" | | | data-sort-value="J99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" | | ||
|- | |- | ||
| data-sort-value="K01" | K1 || N || VD_VINT0 || | | data-sort-value="K01" | K1 || N || VD_VINT0 || ? || | ||
|- | |- | ||
| data-sort-value="K02" | K2 || N || VD_VINT1 || | | data-sort-value="K02" | K2 || N || VD_VINT1 || ? || | ||
|- | |- | ||
| data-sort-value="K03" | K3 || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" style="color:#888" | Missing pad | | data-sort-value="K03" | K3 || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" style="color:#888" | Missing pad | ||
Line 335: | Line 335: | ||
| data-sort-value="K09" | K9 || data-sort-value="ZJ" | JTAG || JTDO || ? || Connected to [[Service_Connectors#CN4009| service connector]] (CN4009) pin 6 | | data-sort-value="K09" | K9 || data-sort-value="ZJ" | JTAG || JTDO || ? || Connected to [[Service_Connectors#CN4009| service connector]] (CN4009) pin 6 | ||
|- | |- | ||
| data-sort-value="K10" | K10 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || | | data-sort-value="K10" | K10 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || DVDD || {{pini}} || data-sort-value="ZV18" style="color:#888" | +1.8V_EVER | ||
|- | |- | ||
| data-sort-value="K11" | K11 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || {{cellcolors|#333|#fff}} VSSF || {{pini}} || data-sort-value="ZG" style="color:#888" | Ground | | data-sort-value="K11" | K11 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || {{cellcolors|#333|#fff}} VSSF || {{pini}} || data-sort-value="ZG" style="color:#888" | Ground | ||
Line 353: | Line 353: | ||
| data-sort-value="L01" | L1 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || {{cellcolors|#333|#fff}} VSS || {{pini}} || data-sort-value="ZG" style="color:#888" | Ground | | data-sort-value="L01" | L1 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || {{cellcolors|#333|#fff}} VSS || {{pini}} || data-sort-value="ZG" style="color:#888" | Ground | ||
|- | |- | ||
| data-sort-value="L02" | L2 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || | | data-sort-value="L02" | L2 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || VDD0 || {{pini}} || data-sort-value="ZV12" style="color:#888" | +1.2V_MC2_VDDIO | ||
|- | |- | ||
| data-sort-value="L03" | L3 || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" style="color:#888" | Missing pad | | data-sort-value="L03" | L3 || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" style="color:#888" | Missing pad | ||
Line 361: | Line 361: | ||
| data-sort-value="L05" | L5 || L || PL7 || {{pinnc}} || data-sort-value="ZNC" style="color:#888" | Not Connected | | data-sort-value="L05" | L5 || L || PL7 || {{pinnc}} || data-sort-value="ZNC" style="color:#888" | Not Connected | ||
|- | |- | ||
| data-sort-value="L06" | L6 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || | | data-sort-value="L06" | L6 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || VDDF || {{pini}} || data-sort-value="ZV33" style="color:#888" | +3.3V_EVER | ||
|- | |- | ||
| data-sort-value="L07" | L7 || data-sort-value="ZJ" | JTAG || JNTRST || ? || Connected to [[Service_Connectors#CN4009| service connector]] (CN4009) pin 2 ? | | data-sort-value="L07" | L7 || data-sort-value="ZJ" | JTAG || JNTRST || ? || Connected to [[Service_Connectors#CN4009| service connector]] (CN4009) pin 2 ? | ||
Line 369: | Line 369: | ||
| data-sort-value="L09" | L9 || data-sort-value="ZJ" | JTAG || JTMS || ? || Connected to [[Service_Connectors#CN4009| service connector]] (CN4009) pin 7 | | data-sort-value="L09" | L9 || data-sort-value="ZJ" | JTAG || JTMS || ? || Connected to [[Service_Connectors#CN4009| service connector]] (CN4009) pin 7 | ||
|- | |- | ||
| data-sort-value="L10" | L10 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || | | data-sort-value="L10" | L10 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || DVDD || {{pini}} || data-sort-value="ZV18" style="color:#888" | +1.8V_EVER | ||
|- | |- | ||
| data-sort-value="L11" | L11 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || | | data-sort-value="L11" | L11 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || DVDD || {{pini}} || data-sort-value="ZV18" style="color:#888" | +1.8V_EVER | ||
|- | |- | ||
| data-sort-value="L12" | L12 || C || RSXVRM_VID4 || {{pino}} || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6201) pin 3 | | data-sort-value="L12" | L12 || C || RSXVRM_VID4 || {{pino}} || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6201) pin 3 | ||
Line 393: | Line 393: | ||
| data-sort-value="M04" | M4 || A || PA0 || {{pinnc}} || data-sort-value="ZNC" style="color:#888" | Not Connected (CL4092) | | data-sort-value="M04" | M4 || A || PA0 || {{pinnc}} || data-sort-value="ZNC" style="color:#888" | Not Connected (CL4092) | ||
|- | |- | ||
| data-sort-value="M05" | M5 || A || WLAN_RESET || | | data-sort-value="M05" | M5 || A || WLAN_RESET || ? || Connected to wifi board connector (CN3701) pin 29 (named 11G_RESET). This is a syscon output | ||
|- | |- | ||
| data-sort-value="M06" | M6 || A || PA4 || {{pinnc}} || data-sort-value="ZNC" style="color:#888" | Not Connected (CL4087) | | data-sort-value="M06" | M6 || A || PA4 || {{pinnc}} || data-sort-value="ZNC" style="color:#888" | Not Connected (CL4087) | ||
Line 401: | Line 401: | ||
| data-sort-value="M08" | M8 || G || FANPWM1 || ? || Secondary fan output (non-retail PS3 models only) | | data-sort-value="M08" | M8 || G || FANPWM1 || ? || Secondary fan output (non-retail PS3 models only) | ||
|- | |- | ||
| data-sort-value="M09" | M9 || G || BUZZER || | | data-sort-value="M09" | M9 || G || BUZZER || ? || | ||
|- | |- | ||
| data-sort-value="M10" | M10 || G || XDR_FET_VREF || | | data-sort-value="M10" | M10 || G || XDR_FET_VREF || ? || Connected to transistor DTC144EUA-T106 (Q4008). Switches XDR_RQ_VREF_FET | ||
|- | |- | ||
| data-sort-value="M11" | M11 || G || SW_ATA || ? || Connected to UMH2NTN dual transistor (Q6009) pin 2 (switches +12V_BD)<br>Connected to UMH2NTN dual transistor (Q6009) pin 5 (switches +5V_BD)<br>Connected to UMH2NTN dual transistor (Q6006) pin 2 (switches +5V_HDD) | | data-sort-value="M11" | M11 || G || SW_ATA || ? || Connected to UMH2NTN dual transistor (Q6009) pin 2 (switches +12V_BD)<br>Connected to UMH2NTN dual transistor (Q6009) pin 5 (switches +5V_BD)<br>Connected to UMH2NTN dual transistor (Q6006) pin 2 (switches +5V_HDD) | ||
Line 427: | Line 427: | ||
| data-sort-value="N04" | N4 || A || SW_5_A || ? || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6201) pin 29<br>Connected to [[Components#Toshiba_TC7SG08FU_.282_Input_AND_Gate.29|Toshiba TC7SG08FU]] (IC6204) pin 1<br>Switches +1.2V_RSX_VDDC | | data-sort-value="N04" | N4 || A || SW_5_A || ? || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6201) pin 29<br>Connected to [[Components#Toshiba_TC7SG08FU_.282_Input_AND_Gate.29|Toshiba TC7SG08FU]] (IC6204) pin 1<br>Switches +1.2V_RSX_VDDC | ||
|- | |- | ||
| data-sort-value="N05" | N5 || A || BT_RESET || | | data-sort-value="N05" | N5 || A || BT_RESET || ? || Connected to wifi board connector (CN3701) pin 10 (named SYSCON_RST). This is a syscon output | ||
|- | |- | ||
| data-sort-value="N06" | N6 || A || AUDIO_MUTE || ? || Connected to transistor DTA144EUA-T106 (Q2404). Switches [[Components#Cirrus_CX4351-CZZR|Cirrus CX4351-CZZR]] pin 18 (AOUTA) left audio channel and pin 15 (AOUTB) right audio channel, that are connected to [[Connectors#AV_Multi_Out_pinout_-_CN2401_12P|MultiAV connector]] pin 11 (AUL) and pin9 (AUR) respectivelly | | data-sort-value="N06" | N6 || A || AUDIO_MUTE || ? || Connected to transistor DTA144EUA-T106 (Q2404). Switches [[Components#Cirrus_CX4351-CZZR|Cirrus CX4351-CZZR]] pin 18 (AOUTA) left audio channel and pin 15 (AOUTB) right audio channel, that are connected to [[Connectors#AV_Multi_Out_pinout_-_CN2401_12P|MultiAV connector]] pin 11 (AUL) and pin9 (AUR) respectivelly | ||
Line 437: | Line 437: | ||
| data-sort-value="N09" | N9 || G || SW_PWM || ? || Connected to [[Switch_boards|Switch board]] [[CSW-001]] connector pin 2 | | data-sort-value="N09" | N9 || G || SW_PWM || ? || Connected to [[Switch_boards|Switch board]] [[CSW-001]] connector pin 2 | ||
|- | |- | ||
| data-sort-value="N10" | N10 || G || XDR_FET_SCK || | | data-sort-value="N10" | N10 || G || XDR_FET_SCK || ? || BE_RQ_SCK_BJT | ||
|- | |- | ||
| data-sort-value="N11" | N11 || G || SW_4_A || | | data-sort-value="N11" | N11 || G || SW_4_A || ? || Connected to wifi board connector (CN3701) pin 9 (named 11G_PWR_EN). This is a syscon output<br>Connected to base pin of transistor UMH2NTN (Q3501) who switches IC3502 pin 5, and IC3501 pin 3 (+1.2V_ESW, +1.9V_ESW, +3.3V_ESW for Ethernet Controller) | ||
|- | |- | ||
| data-sort-value="N12" | N12 || C || RSXVRM_VID0 || {{pino}} || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6201) pin 31 | | data-sort-value="N12" | N12 || C || RSXVRM_VID0 || {{pino}} || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6201) pin 31 | ||
Line 491: | Line 491: | ||
| data-sort-value="R02" | R2 || M || PM6 || {{pinnc}} || data-sort-value="ZNC" style="color:#888" | Not Connected (CL4010) | | data-sort-value="R02" | R2 || M || PM6 || {{pinnc}} || data-sort-value="ZNC" style="color:#888" | Not Connected (CL4010) | ||
|- | |- | ||
| data-sort-value="R03" | R3 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || | | data-sort-value="R03" | R3 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || VDD1 || {{pini}} || data-sort-value="ZV12" style="color:#888" | +1.2V_MC2_VDDIO | ||
|- | |- | ||
| data-sort-value="R04" | R4 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || {{cellcolors|#333|#fff}} AVSUO || {{pini}} || data-sort-value="ZG" style="color:#888" | Ground | | data-sort-value="R04" | R4 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || {{cellcolors|#333|#fff}} AVSUO || {{pini}} || data-sort-value="ZG" style="color:#888" | Ground | ||
|- | |- | ||
| data-sort-value="R05" | R5 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || | | data-sort-value="R05" | R5 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || AVDUO || {{pini}} || data-sort-value="ZV33" style="color:#888" | +3.3V_EVER | ||
|- | |- | ||
| data-sort-value="R06" | R6 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || {{cellcolors|#333|#fff}} VSS || {{pini}} || data-sort-value="ZG" style="color:#888" | Ground | | data-sort-value="R06" | R6 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || {{cellcolors|#333|#fff}} VSS || {{pini}} || data-sort-value="ZG" style="color:#888" | Ground | ||
|- | |- | ||
| data-sort-value="R07" | R7 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || | | data-sort-value="R07" | R7 || data-sort-value="ZP" | <abbr title="Power port>PWR</abbr> || DVDD || {{pini}} || data-sort-value="ZV18" style="color:#888" | +1.8V_EVER | ||
|- | |- | ||
| data-sort-value="R08" | R8 || Q || RSX_FBVDD_SEL || {{pino}} || Connected to [[Components#Texas_Instruments_SN105233DBTR|Texas Instruments SN105233DBTR]] (IC6301) through transistor/s | | data-sort-value="R08" | R8 || Q || RSX_FBVDD_SEL || {{pino}} || Connected to [[Components#Texas_Instruments_SN105233DBTR|Texas Instruments SN105233DBTR]] (IC6301) through transistor/s | ||
Line 507: | Line 507: | ||
| data-sort-value="R10" | R10 || Q || RMC_IN || ? || Connected to [[Switch_boards|Switch board]] [[CSW-001]] connector pin 3<br> Connected to [[Service_Connectors#CN4009| service connector]] (CN4009) pin 17 | | data-sort-value="R10" | R10 || Q || RMC_IN || ? || Connected to [[Switch_boards|Switch board]] [[CSW-001]] connector pin 3<br> Connected to [[Service_Connectors#CN4009| service connector]] (CN4009) pin 17 | ||
|- | |- | ||
| data-sort-value="R11" | R11 || B || VD_CECO0 || | | data-sort-value="R11" | R11 || B || VD_CECO0 || ? || | ||
|- | |- | ||
| data-sort-value="R12" | R12 || B || SW_3 || ? || Connected to [[Regulators#Rohm_BD3520FVM-TR_.28Single_channel_Regulator_Driver_IC.29|Rohm BD3520FVM-TR]] (IC6305) pin 3 (switches +1.2V_SB_VDDC and +1.2V_SB_VDDR) | | data-sort-value="R12" | R12 || B || SW_3 || ? || Connected to [[Regulators#Rohm_BD3520FVM-TR_.28Single_channel_Regulator_Driver_IC.29|Rohm BD3520FVM-TR]] (IC6305) pin 3 (switches +1.2V_SB_VDDC and +1.2V_SB_VDDR) | ||
Line 535: | Line 535: | ||
| data-sort-value="T07" | T7 || data-sort-value="ZC" | <abbr title="Reset & Clock">CLK</abbr> || XXTALO || {{pinnc}} || data-sort-value="ZNC" style="color:#888" | Not Connected (CL4040) | | data-sort-value="T07" | T7 || data-sort-value="ZC" | <abbr title="Reset & Clock">CLK</abbr> || XXTALO || {{pinnc}} || data-sort-value="ZNC" style="color:#888" | Not Connected (CL4040) | ||
|- | |- | ||
| data-sort-value="T08" | T8 || Q || THR_I2C_SCL || | | data-sort-value="T08" | T8 || Q || THR_I2C_SCL || ? || | ||
|- | |- | ||
| data-sort-value="T09" | T9 || Q || THR_I2C_SDA || | | data-sort-value="T09" | T9 || Q || THR_I2C_SDA || ? || | ||
|- | |- | ||
| data-sort-value="T10" | T10 || Q || PQ4 || {{pinnc}} || data-sort-value="ZNC" style="color:#888" | Not Connected (CL4021) | | data-sort-value="T10" | T10 || Q || PQ4 || {{pinnc}} || data-sort-value="ZNC" style="color:#888" | Not Connected (CL4021) | ||
Line 543: | Line 543: | ||
| data-sort-value="T11" | T11 || Q || PQ5 || {{pinnc}} || data-sort-value="ZNC" style="color:#888" | Not Connected (CL4022) | | data-sort-value="T11" | T11 || Q || PQ5 || {{pinnc}} || data-sort-value="ZNC" style="color:#888" | Not Connected (CL4022) | ||
|- | |- | ||
| data-sort-value="T12" | T12 || B || VD_CECO1 || | | data-sort-value="T12" | T12 || B || VD_CECO1 || ? || | ||
|- | |- | ||
| data-sort-value="T13" | T13 || B || SW_4_B || ? || Connected to 88E6108 ethernet controller (IC3503) pin 94 (signal named P3_ENABLE_PD)<br>Connected to (Q6003) transistor (switches +3.3V_SB_VDDIO)<br>Connected to [[Regulators#OnSemi_NCP511SN25T1G_.282.5V_150_mA_CMOS_Low_Iq_Low-Dropout_Voltage_Regulator.29 | OnSemi NCP511SN25T1G]] (IC6011) pin 3 (switches +2.5V_SB_PLL_VDDC)<br>Connected to [[Regulators#Mitsumi_MM1591JFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591JFBEG]] (IC6014) pin 5 (switches +1.8V_SB_PERI)<br>Connected to UMH2NTN dual transistor (Q6006) pin 5 (switches +5V_USB) | | data-sort-value="T13" | T13 || B || SW_4_B || ? || Connected to 88E6108 ethernet controller (IC3503) pin 94 (signal named P3_ENABLE_PD)<br>Connected to (Q6003) transistor (switches +3.3V_SB_VDDIO)<br>Connected to [[Regulators#OnSemi_NCP511SN25T1G_.282.5V_150_mA_CMOS_Low_Iq_Low-Dropout_Voltage_Regulator.29 | OnSemi NCP511SN25T1G]] (IC6011) pin 3 (switches +2.5V_SB_PLL_VDDC)<br>Connected to [[Regulators#Mitsumi_MM1591JFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591JFBEG]] (IC6014) pin 5 (switches +1.8V_SB_PERI)<br>Connected to UMH2NTN dual transistor (Q6006) pin 5 (switches +5V_USB) |