Editing Template:Syscon pinout BGA 200 pads
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| data-sort-value="E05" | E5 || O || PO0 || {{pinnc}} || data-sort-value="ZNC" style="color:#888" | Not Connected (CL4086) | | data-sort-value="E05" | E5 || O || PO0 || {{pinnc}} || data-sort-value="ZNC" style="color:#888" | Not Connected (CL4086) | ||
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| data-sort-value="E06" | E6 || H || HDMI_INT || | | data-sort-value="E06" | E6 || H || HDMI_INT || ? || Connected to [[TC7WP3125FK]] (IC2501) pin 6. This is a syscon input at 3.3V<br> The [[TC7WP3125FK]] converts the signal originally triggered by [[Sil9132CBU]] pad E10 ? at 1.5V and converts it to 3.3V for syscon<br>The [[TC7WP3125FK]] also converts the signal RS_SPDO0 (at 1.5V) into RS_SPDO0_33 (at 3.3V) | ||
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| data-sort-value="E07" | E7 || H || MECHA_INT || ? || Not connected in retail PS3 models (testpad CL4102). The related SouthBridge pad is tied to GND with a 10k resistor (R3163) | | data-sort-value="E07" | E7 || H || MECHA_INT || ? || Not connected in retail PS3 models (testpad CL4102). The related SouthBridge pad is tied to GND with a 10k resistor (R3163) | ||
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| data-sort-value="E11" | E11 || F || SB_CGRESET || ? || SB_CGRST (the name indicates that it resets the clock generator for the southbridge) | | data-sort-value="E11" | E11 || F || SB_CGRESET || ? || SB_CGRST (the name indicates that it resets the clock generator for the southbridge) | ||
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| data-sort-value="E12" | E12 || F || BT_WAKEON || | | data-sort-value="E12" | E12 || F || BT_WAKEON || ? || Connected to wifi board connector (CN3701) pin 30 (named BT_WAKE). This is a syscon input | ||
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| data-sort-value="E13" | E13 || F || PF1<br>BE_VCS_1.30_ON || ? || [[COK-001]]/[[COK-002]] PF1 (Not connected)<br>[[SEM-001]] BE_VCS_1.30_ON | | data-sort-value="E13" | E13 || F || PF1<br>BE_VCS_1.30_ON || ? || [[COK-001]]/[[COK-002]] PF1 (Not connected)<br>[[SEM-001]] BE_VCS_1.30_ON | ||
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| data-sort-value="M04" | M4 || A || PA0 || {{pinnc}} || data-sort-value="ZNC" style="color:#888" | Not Connected (CL4092) | | data-sort-value="M04" | M4 || A || PA0 || {{pinnc}} || data-sort-value="ZNC" style="color:#888" | Not Connected (CL4092) | ||
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| data-sort-value="M05" | M5 || A || WLAN_RESET || | | data-sort-value="M05" | M5 || A || WLAN_RESET || ? || Connected to wifi board connector (CN3701) pin 29 (named 11G_RESET). This is a syscon output | ||
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| data-sort-value="M06" | M6 || A || PA4 || {{pinnc}} || data-sort-value="ZNC" style="color:#888" | Not Connected (CL4087) | | data-sort-value="M06" | M6 || A || PA4 || {{pinnc}} || data-sort-value="ZNC" style="color:#888" | Not Connected (CL4087) | ||
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| data-sort-value="N04" | N4 || A || SW_5_A || ? || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6201) pin 29<br>Connected to [[Components#Toshiba_TC7SG08FU_.282_Input_AND_Gate.29|Toshiba TC7SG08FU]] (IC6204) pin 1<br>Switches +1.2V_RSX_VDDC | | data-sort-value="N04" | N4 || A || SW_5_A || ? || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6201) pin 29<br>Connected to [[Components#Toshiba_TC7SG08FU_.282_Input_AND_Gate.29|Toshiba TC7SG08FU]] (IC6204) pin 1<br>Switches +1.2V_RSX_VDDC | ||
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| data-sort-value="N05" | N5 || A || BT_RESET || | | data-sort-value="N05" | N5 || A || BT_RESET || ? || Connected to wifi board connector (CN3701) pin 10 (named SYSCON_RST). This is a syscon output | ||
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| data-sort-value="N06" | N6 || A || AUDIO_MUTE || ? || Connected to transistor DTA144EUA-T106 (Q2404). Switches [[Components#Cirrus_CX4351-CZZR|Cirrus CX4351-CZZR]] pin 18 (AOUTA) left audio channel and pin 15 (AOUTB) right audio channel, that are connected to [[Connectors#AV_Multi_Out_pinout_-_CN2401_12P|MultiAV connector]] pin 11 (AUL) and pin9 (AUR) respectivelly | | data-sort-value="N06" | N6 || A || AUDIO_MUTE || ? || Connected to transistor DTA144EUA-T106 (Q2404). Switches [[Components#Cirrus_CX4351-CZZR|Cirrus CX4351-CZZR]] pin 18 (AOUTA) left audio channel and pin 15 (AOUTB) right audio channel, that are connected to [[Connectors#AV_Multi_Out_pinout_-_CN2401_12P|MultiAV connector]] pin 11 (AUL) and pin9 (AUR) respectivelly | ||
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| data-sort-value="N10" | N10 || G || XDR_FET_SCK || {{pino}} || Connected to transistor SST222AT116 (Q1302) BE_RQ_SCK_BJT | | data-sort-value="N10" | N10 || G || XDR_FET_SCK || {{pino}} || Connected to transistor SST222AT116 (Q1302) BE_RQ_SCK_BJT | ||
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| data-sort-value="N11" | N11 || G || SW_4_A || | | data-sort-value="N11" | N11 || G || SW_4_A || ? || Connected to wifi board connector (CN3701) pin 9 (named 11G_PWR_EN). This is a syscon output<br>Connected to base pin of transistor UMH2NTN (Q3501) who switches IC3502 pin 5, and IC3501 pin 3 (+1.2V_ESW, +1.9V_ESW, +3.3V_ESW for Ethernet Controller) | ||
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| data-sort-value="N12" | N12 || C || RSXVRM_VID0 || {{pino}} || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6201) pin 31 | | data-sort-value="N12" | N12 || C || RSXVRM_VID0 || {{pino}} || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6201) pin 31 |