Editing Template:Elpida memory product code
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{| class="wikitable" style=" | {| class="wikitable" style="margin:auto" | ||
|+Elpida | |+Elpida XDR DRAM part number decoder {{ed right|Elpida XDR DRAM part number decoder}} | ||
! Product Family !! Density !! Organization !! Power Supply, Interface !! Die Rev. !! Package !! Speed !! Internal Code | ! Product Family !! Density !! Organization !! Power Supply, Interface !! Die Rev. !! Package !! Speed !! Internal Code !! Enviroment Code | ||
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| '''X''': XDR DRAM | | '''X''': XDR DRAM | ||
| '''51''': 512M<br />'''10''': 1Gb | | '''51''': 512M<br />'''10''': 1Gb | ||
| '''16''': x16bit<br />'''32''': x32bit | | '''16''': x16bit<br />'''32''': x32bit | ||
| '''A''': 1.8V, DRSL<br />'''B''': 1.5V +/- 0.075V, DRSL | | '''A''': 1.8V, DRSL<br />'''B''': 1.5V +/- 0.075V, DRSL | ||
| '''A''': Rev1<br />'''B''': Rev2<br />'''C''': Rev3<br />'''D''': Rev4 | | '''A''': Rev1<br />'''B''': Rev2<br />'''C''': Rev3<br />'''D''': Rev4 | ||
| '''SE''': FBGA<br />'''BG''': FBGA | | '''SE''': FBGA<br />'''BG''': FBGA ? | ||
| '''3C''': 3.2Gbps (tRAC = 35ns, C Bin)<br />'''4D''': 4.0Gbps (tRAC = 34ns, D Bin) | | '''3C''': 3.2Gbps (tRAC = 35ns, C Bin)<br />'''4D''': 4.0Gbps (tRAC = 34ns, D Bin) | ||
| '''A2''': | | '''A2''': unknown | ||
| '''E''': Lead Free<br />'''F''': Lead & Halogen Free | | '''E''': Lead Free<br />'''F''': Lead & Halogen Free | ||
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|} | |} | ||
<noinclude>[[Category:Templates]]</noinclude> | <noinclude>[[Category:Templates]]</noinclude> | ||