Editing Template:CELL pad layout 65nm
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The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then publish the changes below to finish undoing the edit.
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{| class="wikitable mw-datatable sortable" style="width:100%; line-height:1em; font-size:0.9em" | {| class="wikitable mw-datatable sortable" style="width:100%; line-height:1.1em; font-size:0.9em" | ||
|+{{captionlinks|CELL pad layout 65nm}} | |+ {{captionlinks|CELL pad layout 65nm}} | ||
! Pad !! colspan="2" | Name !! style="padding: | ! style="border-bottom:hidden; padding:2px" | Pad !! colspan="2" | Name !! style="border-bottom:hidden; padding:2px" | Type !! style="border-bottom:hidden" | Description | ||
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! style="border-top:hidden; background-position:50%" | !! style="padding-right:0px" | Internal !! style="padding-right:0px" | External !! style="border-top:hidden; background-position:50%" | !! style="border-top:hidden; background-position:50%" | | ! style="border-top:hidden; padding:0px; background-position:50%" | !! style="width:25px; min-width:25px; padding-right:0px" | Internal !! style="width:25px; min-width:25px; padding-right:0px" | External !! style="border-top:hidden; background-position:50%" | !! style="border-top:hidden; background-position:50%" | | ||
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| data-sort-value="0A01" | A1 || | | data-sort-value="0A01" | A1 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3 | ||
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| data-sort-value="0A02" | A2 || || || | | data-sort-value="0A02" | A2 || || || || | ||
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| data-sort-value="0A10" | A10 || || || || | | data-sort-value="0A10" | A10 || || || || |