Editing Talk:RAM
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: without actual tweet hard to discuss... It is in the nature of /XDR/ RAM to be Random Accessable Memory in the first place ;) As long as you stick to that one module at a time. There is no HV/W^X etc on that hardware level (which takes place in the CPU / OS instead) [[User:Euss|Euss]] ([[User talk:Euss|talk]]) 12:13, 27 August 2014 (EDT) | : without actual tweet hard to discuss... It is in the nature of /XDR/ RAM to be Random Accessable Memory in the first place ;) As long as you stick to that one module at a time. There is no HV/W^X etc on that hardware level (which takes place in the CPU / OS instead) [[User:Euss|Euss]] ([[User talk:Euss|talk]]) 12:13, 27 August 2014 (EDT) | ||
:: sorry about that, should've taken a picture :P i'm not as fast as you when you're awake :) 17:36, 27 August 2014 [[User:Zecoxao]] | :: sorry about that, should've taken a picture :P i'm not as fast as you when you're awake :) 17:36, 27 August 2014 [[User:Zecoxao]] | ||