Editing RAM
Jump to navigation
Jump to search
The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then publish the changes below to finish undoing the edit.
Latest revision | Your text | ||
Line 1: | Line 1: | ||
= System Memory (RAM) = | = Main System Memory (RAM) = | ||
<div style="float:right">[[File:XDR-quad to CELLBE to SouthBridge diagram.png|200px|thumb|left|XDR-quad to CELLBE to SouthBridge diagram of PS3 FAT and early PS3 Slim's CECH-20..A/DYN-001]]<br />[[File:XDR-dual to CELLBE to SouthBridge diagram.png|200px|thumb|left|XDR-dual to CELLBE to SouthBridge diagram since CECH-21..A/SUR-001]]<br />[[File:X5116AC-3C-E.jpg|200px|thumb|left|XDR-quad memory<br />[[CECHGxx]] / [[SEM-00x|SEM-001]]]]</div> | |||
== Chipnumers @ SKU's == | == Chipnumers @ SKU's == | ||
The PS3 has 256MB of 64 bit bus Rambus XDR main system memory. Older models use four 64MB chips, while newer models uses two 128MB chips. | |||
The PS3 has | |||
{|class="wikitable | {|class="wikitable" | ||
|- | |- | ||
! PS3 Model !! Mobo Model !! RAM Serial !! Amount !! Notes | ! PS3 Model !! Mobo Model !! Mobo serial !! RAM Serial !! Amount !! Notes | ||
|- | |- | ||
| [[CECHAxx | | [[CECHAxx]] || [[COK-00x#COK-001|COK-001]] || 1-871-868-12<br />1-871-868-22<br />1-871-868-32 || [[X5116ACSE-3C-E]]<br /> or<br />[[K4Y50164UC-JCB3 ]] || style="text-align:center;" | 4 || | ||
|- | |- | ||
| [[ | | [[CECHBxx]] || [[COK-00x#COK-001|COK-001]] || 1-871-868-12<br />1-871-868-22<br />1-871-868-32 || [[X5116ACSE-3C-E]]<br /> or<br />[[K4Y50164UC-JCB3 ]] || style="text-align:center;" | 4 || | ||
|- | |- | ||
| [[ | | [[CECHCxx]] || [[COK-00x#COK-002|COK-002]] || 1-873-513-21<br />1-873-513-31 || [[X5116ACSE-3C-E]]<br /> or<br />[[K4Y50164UC-JCB3 ]] || style="text-align:center;" | 4 || | ||
|- | |- | ||
| | | style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">[[CECHDxx]]</span> || colspan="6" style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">SKU never released</span> | ||
|- | |- | ||
| [[ | | [[CECHExx]] || [[COK-00x#COK-002W|COK-002W]] || || [[X5116ACSE-3C-E]]<br /> or<br />[[K4Y50164UC-JCB3 ]] || style="text-align:center;" | 4 || | ||
|- | |- | ||
| | | style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">[[CECHFxx]]</span> || colspan="6" style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">SKU never released</span> | ||
|- | |- | ||
| [[ | | [[CECHGxx]] || [[SEM-00x|SEM-001]] || 1-875-384-21<br />1-875-384-31 || [[X5116ACSE-3C-E]] || style="text-align:center;" | 4 || | ||
|- | |- | ||
| [[ | | [[CECHHxx]] || [[DIA-00x#DIA-001|DIA-001]] || 1-875-368-11<br />1-875-368-31 || [[X5116ADSE-3C-E]] || style="text-align:center;" | 4 || | ||
|- | |- | ||
| | | style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">[[CECHIxx]]</span> || colspan="6" style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">SKU never released</span> | ||
|- | |- | ||
| [[ | | [[CECHJxx]] || [[DIA-00x#DIA-002|DIA-002]] || 1-876-912-32 || [[K4Y50164UE-JCB3]] || style="text-align:center;" | 4 || | ||
|- | |- | ||
| | | [[CECHKxx]] || [[DIA-00x#DIA-002|DIA-002]] || 1-876-912-32 || [[K4Y50164UE-JCB3]] || style="text-align:center;" | 4 || | ||
|- | |- | ||
| [[ | | [[CECHLxx]] || [[VER-00x|VER-001]] || 1-878-196-31<br />1-878-196-41 || [[X5116ADSE-3C-E]]<br /> or<br />[[IDRD51-0-A1F1C-32C]] || style="text-align:center;" | 4 || | ||
|- | |- | ||
| [[ | | [[CECHMxx]] || [[VER-00x|VER-001]] || 1-878-196-31<br />1-878-196-41 || [[X5116ADSE-3C-E]] || style="text-align:center;" | 4 || | ||
|- | |- | ||
| | | style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">[[CECHNxx]]</span> || colspan="6" style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">SKU never released</span> | ||
|- | |- | ||
| | | style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">[[CECHOxx]]</span> || colspan="6" style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">SKU never released</span> | ||
|- | |- | ||
| | | [[CECHPxx]] || [[VER-00x|VER-001]] || 1-878-196-31<br />1-878-196-41 || [[X5116ADSE-3C-E]] || style="text-align:center;" | 4 || | ||
|- | |- | ||
| [[ | | [[CECHQxx]] || [[VER-00x|VER-001]] || 1-878-196-31<br />1-878-196-41 || [[X5116ADSE-3C-E]] || style="text-align:center;" | 4 || | ||
|- | |- | ||
| [[CECH- | | [[CECH-20xx]] || [[DYN-00x|DYN-001]] || 1-880-055-31 || [[X5116ADSE-3C-E]] || style="text-align:center;" | 4 || | ||
|- | |- | ||
| [[CECH- | | [[CECH-21xx]] || [[SUR-00x|SUR-001]] || 1-881-945-11 || [[X1032BASE-3C-F]] || style="text-align:center;" | 2 || | ||
|- | |- | ||
| [[CECH- | | [[CECH-25xx]] || [[JTP-00x|JTP-001]] || 1-882-481-31 || [[X1032BASE-3C-F#Elpida X1032BASE-3CA2-F|X1032BASE-3CA2-F ]] || style="text-align:center;" | 2 || | ||
|- | |- | ||
| [[CECH- | | [[CECH-25xx]] || [[JSD-00x|JSD-001]] || 1-882-770-11 || [[X1032BASE-3C-F]] || style="text-align:center;" | 2 || | ||
|- | |- | ||
| | | [[CECH-30xx]] || [[KTE-00x|KTE-001]] || 1-884-749-11 || [[X1032BASE-3C-F]] || style="text-align:center;" | 2 || | ||
|- | |- | ||
| [[CECH- | | [[CECH-40xx]] || [[MSX-00x|MSX-001]] || 1-886-928-11 || [[X1032BBBG-3C-F]] || style="text-align:center;" | 2 || | ||
|- | |||
| [[CECH-40xx]] || [[MPX-00x|MPX-001]] || 1-887-233-11 || [[X1032BBBG-3C-F]] || style="text-align:center;" | 2 || | |||
|- | |- | ||
|} | |} | ||
Line 81: | Line 82: | ||
|- | |- | ||
|} | |} | ||
: | |||
== | == Graphics Memory == | ||
<div style="float:right">[[File:GDDR3 to RSX to CellBE diagram.png|200px|thumb|left|Quad 64MB GDDR3 (256MB total) to RSX to CellBE diagram ]]<br />[[File:RSX_MEMORY.jpg|200px|thumb|left|RSX bare die<br />GPU in centre<br />4x GDDR3]]</div> | |||
<div style="float:right">[[File:GDDR3 to RSX to CellBE diagram.png| | |||
The 256MB of GDDR3 memory is located inside the [[RSX]] chip using four 64MB FBGA chips. | The 256MB of GDDR3 memory is located inside the [[RSX]] chip using four 64MB FBGA chips. | ||
Line 119: | Line 105: | ||
|} | |} | ||
= | <div style="height:255px; overflow:auto"><!--// dirty and cheap spacer //--></div> | ||
[https:// | |||
== Other XDR Rambus references == | |||
* [https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/AF7832F379790768872572D10047E52B/$file/CellBE_HIG_65nm_v1.01_8Jun2007.pdf CellBE_HIG_65nm_v1.01_8Jun2007.pdf] | |||
* [http://www.capsl.udel.edu/~jmanzano/Cell/docs/arch/BE_Hardwar_Init_Guide_v1.3_31March2006.pdf BE_Hardwar_Init_Guide_v1.3_31March2006.pdf] | |||
* [http://www.rambus.com/assets/documents/products/dl_0362_v0_71.pdf Rambus XDR IO Cell (XIO) - dl_0362_v0_71.pdf] | |||
* [http://www.rambus.com/assets/documents/products/dl_0161_v0_8.pdf XDR Architecture - Rambus dl_0161_v0_8.pdf] | |||
* [http://www.rambus.com/assets/documents/products/xdr_dl_0476.pdf 8x4Mx16/8/4/2 - Rambus xdr_dl_0476.pdf] | |||
* [http://www.rambus.com/assets/documents/products/dl_0169l_v0_81.pdf XDR Clock Generator - Rambus dl_0169l_v0_81.pdf] | |||
* dl_0178_v0_93.pdf (january 2006) | |||
* dl_0178_v0_95.pdf (august 2006) | |||
* http://www.mirrorcreator.com/files/1KD96OYT/xdr_product_guide_mar_06_0.pdf_links | |||
* http://www.mirrorcreator.com/files/1C1NTTYD/Elpida_E1819E20_0.pdf_links | |||
* http://www.mirrorcreator.com/files/KGNOVWHK/Elpida_E0881E20_0.pdf_links | |||
* http://www.mirrorcreator.com/files/SSF2GNEK/Samsung_k4y50xx4ue_rev10.pdf_links | |||
* http://www.mirrorcreator.com/files/1FQRE8S5/Samsung_k4y50xx4uc_rev11_0.pdf_links | |||
* http://www.mirrorcreator.com/files/11S5L1EW/Elpida_E1033E40_EOL_0.pdf_links | |||
== PS2 Compatibility Memory == | |||
See: [[PS2 Compatibility]] | See: [[PS2 Compatibility]] | ||
{{Motherboard Components}}<noinclude>[[Category:Main]]</noinclude> | {{Motherboard Components}}<noinclude>[[Category:Main]]</noinclude> |