Editing RAM

Jump to navigation Jump to search
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then publish the changes below to finish undoing the edit.

Latest revision Your text
Line 1: Line 1:
= System Memory (RAM) =
[[Category:Hardware]]
= Main System Memory (RAM) =
<div style="float:right">[[File:XDR-quad to CELLBE to SouthBridge diagram.png|200px|thumb|left|XDR-quad to CELLBE to SouthBridge diagram of PS3 FAT and early PS3 Slim's CECH-20..A/DYN-001]]<br />[[File:XDR-dual to CELLBE to SouthBridge diagram.png|200px|thumb|left|XDR-dual to CELLBE to SouthBridge diagram  since CECH-21..A/SUR-001]]</div>


== Chipnumers @ SKU's ==
== Chipnumers @ SKU's ==
<div style="float:right">[[File:XDR-quad to CELLBE to SouthBridge diagram.png|x250px|thumb|left|XDR-quad to CELLBE to SouthBridge diagram of PS3 FAT and early PS3 Slim's CECH-20..A/DYN-001]][[File:XDR-dual to CELLBE to SouthBridge diagram.png|x250px|thumb|right|XDR-dual to CELLBE to SouthBridge diagram  since CECH-21..A/SUR-001]]<br />[[File:X5116AC-3C-E.jpg|200px|thumb|right|XDR-quad memory<br />[[CECHGxx]] / [[SEM-00x|SEM-001]]]]</div>
The PS3 has 256MB of 64 bit bus Rambus XDR main system memory. Older models use four 64MB chips, while newer models uses two 128MB chips.
The PS3 has a [https://en.wikipedia.org/wiki/Differential_signalling differential signalling] 64 bit bus with 256MB of [https://en.wikipedia.org/wiki/XDR_DRAM Rambus XDR DRAM] main system memory. Older models use four 64MB chips, while newer models uses two 128MB chips.


{|class="wikitable" style="line-height:1.2em; font-size:1em"
{|class="wikitable"
|-
|-
! PS3 Model !! Mobo Model !! RAM Serial !! Amount !! Notes
! PS3 Model !! Mobo Model !! Mobo serial !! RAM Serial !! Amount !! Notes
|-
|-
| [[CECHAxx]]<br>[[CECHBxx]] || [[COK-001]] || [[X5116ACSE-3C-E]]<br />&nbsp;&nbsp;&nbsp;or<br />[[K4Y50164UC-JCB3 ]] || style="text-align:center;" | 4*16bits ||  
| [[CECHAxx]] || [[COK-00x#COK-001|COK-001]] || 1-871-868-12<br />1-871-868-22<br />1-871-868-32 || [[X5116AC-SE-3C-E]]<br />&nbsp;&nbsp;&nbsp;or<br />[[K4Y50164UC-JCB3 ]] || style="text-align:center;" | 4 ||  
|-
|-
| [[CECHCxx]]<br>[[CECHExx]] || [[COK-002]] || [[X5116ACSE-3C-E]]<br />&nbsp;&nbsp;&nbsp;or<br />[[K4Y50164UC-JCB3 ]] || style="text-align:center;" | 4*16bits ||  
| [[CECHBxx]] || [[COK-00x#COK-001|COK-001]] || 1-871-868-12<br />1-871-868-22<br />1-871-868-32 || [[X5116AC-SE-3C-E]]<br />&nbsp;&nbsp;&nbsp;or<br />[[K4Y50164UC-JCB3 ]] || style="text-align:center;" | 4 ||  
|-
|-
| [[CECHGxx]] || [[SEM-001]] || [[X5116ACSE-3C-E]] || style="text-align:center;" | 4*16bits ||  
| [[CECHCxx]] || [[COK-00x#COK-002|COK-002]] || 1-873-513-21<br />1-873-513-31 || [[X5116AC-SE-3C-E]]<br />&nbsp;&nbsp;&nbsp;or<br />[[K4Y50164UC-JCB3 ]] || style="text-align:center;" | 4 ||  
|-
|-
| [[CECHHxx]] || [[DIA-001]] || [[X5116ADSE-3C-E]] || style="text-align:center;" | 4*16bits ||
| style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">[[CECHDxx]]</span> || colspan="6" style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">SKU never released</span>
|-
|-
| [[CECHJxx]]<br>[[CECHKxx]] || [[DIA-002]] || [[K4Y50164UE-JCB3]] || style="text-align:center;" | 4*16bits ||  
| [[CECHExx]] || [[COK-00x#COK-002W|COK-002W]] ||  || [[X5116AC-SE-3C-E]]<br />&nbsp;&nbsp;&nbsp;or<br />[[K4Y50164UC-JCB3 ]] || style="text-align:center;" | 4 ||  
|-
|-
| [[CECHLxx]] || [[VER-001]] || [[X5116ADSE-3C-E]]<br />&nbsp;&nbsp;&nbsp;or<br />[[IDRD51-0-A1F1C-32C]] || style="text-align:center;" | 4*16bits ||
| style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">[[CECHFxx]]</span> || colspan="6" style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">SKU never released</span>
|-
|-
| [[CECHMxx]] || [[VER-001]] || [[X5116ADSE-3C-E]] || style="text-align:center;" | 4*16bits ||  
| [[CECHGxx]] || [[SEM-00x|SEM-001]] || 1-875-384-21<br />1-875-384-31 || [[X5116AC-SE-3C-E]] || style="text-align:center;" | 4 ||  
|-
|-
| [[CECHPxx]] || [[VER-001]] || [[X5116ADSE-3C-E]] || style="text-align:center;" | 4*16bits ||
| [[CECHHxx]] || [[DIA-00x#DIA-001|DIA-001]] || 1-875-368-11<br />1-875-368-31 || [[X5116ADSE-3C-E]] || style="text-align:center;" | 4 ||  
|-
|-
| [[CECHQxx]] || [[VER-001]] || [[X5116ADSE-3C-E]] || style="text-align:center;" | 4*16bits ||
| style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">[[CECHIxx]]</span> || colspan="6" style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">SKU never released</span>
|-
|-
| [[CECH-20xx]] || [[DYN-001]] || [[X5116ADSE-3C-E]] || style="text-align:center;" | 4*16bits ||  
| [[CECHJxx]] || [[DIA-00x#DIA-002|DIA-002]] || 1-876-912-32 || [[K4Y50164UE-JCB3]] || style="text-align:center;" | 4 ||  
|-
|-
| colspan="5" style="padding:0px" |  
| [[CECHKxx]] || [[DIA-00x#DIA-002|DIA-002]] || 1-876-912-32 || [[K4Y50164UE-JCB3]] || style="text-align:center;" | 4 ||  
|-
|-
| [[CECH-21xx]] || [[SUR-001]] || [[X1032BASE-3C-F]] || style="text-align:center;" | 2*32bits ||  
| [[CECHLxx]] || [[VER-00x|VER-001]] || 1-878-196-31<br />1-878-196-41 || [[X5116ADSE-3C-E]]<br />&nbsp;&nbsp;&nbsp;or<br />[[IDRD51-0-A1F1C-32C]] || style="text-align:center;" | 4 ||  
|-
|-
| [[CECH-25xx]] || [[JTP-001]] || [[X1032BASE-3C-F#Elpida X1032BASE-3CA2-F|X1032BASE-3CA2-F ]] || style="text-align:center;" | 2*32bits ||  
| [[CECHMxx]] || [[VER-00x|VER-001]] || 1-878-196-31<br />1-878-196-41 || [[X5116ADSE-3C-E]] || style="text-align:center;" | 4 ||  
|-
|-
| [[CECH-25xx]] || [[JSD-001]] || [[X1032BASE-3C-F]] || style="text-align:center;" | 2*32bits ||
| style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">[[CECHNxx]]</span> || colspan="6" style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">SKU never released</span>
|-
|-
| [[CECH-30xx]] || [[KTE-001]] || [[X1032BASE-3C-F]] || style="text-align:center;" | 2*32bits ||
| style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">[[CECHOxx]]</span> || colspan="6" style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">SKU never released</span>
|-
|-
| colspan="5" style="padding:0px" |  
| [[CECHPxx]] || [[VER-00x|VER-001]] || 1-878-196-31<br />1-878-196-41 || [[X5116ADSE-3C-E]] || style="text-align:center;" | 4 || 
|-
|-
| [[CECH-40xx]] || [[MSX-001]] || [[X1032BBBG-3C-F]] || style="text-align:center;" | 2*32bits ||  
| [[CECHQxx]] || [[VER-00x|VER-001]] || 1-878-196-31<br />1-878-196-41 || [[X5116ADSE-3C-E]] || style="text-align:center;" | 4 ||  
|-
|-
| [[CECH-40xx]] || [[MPX-001]] || [[X1032BBBG-3C-F]] || style="text-align:center;" | 2*32bits ||  
| [[CECH-20xx]] || [[DYN-00x|DYN-001]] || 1-880-055-31 || [[X5116ADSE-3C-E]] || style="text-align:center;" | 4 ||  
|-
|-
| [[CECH-42xx]] || [[NPX-001]] || [[X1032BBBG-3C-F]] || style="text-align:center;" | 2*32bits ||  
| [[CECH-21xx]] || [[SUR-00x|SUR-001]] || 1-881-945-11 || [[X1032BASE-3C-F]] || style="text-align:center;" | 2 ||  
|-
|-
| [[CECH-42xx]] || [[PPX-001]] || || style="text-align:center;" | 2*32bits ||  
| [[CECH-25xx]] || [[JTP-00x|JTP-001]] || 1-882-481-31 || [[X1032BASE-3C-F#Elpida X1032BASE-3CA2-F|X1032BASE-3CA2-F ]] || style="text-align:center;" | 2 ||  
|-
|-
| [[CECH-42xx]] || [[PQX-001]] || [[X1032BBBG-3C-F]] || style="text-align:center;" | 2*32bits ||  
| [[CECH-25xx]] || [[JSD-00x|JSD-001]] || 1-882-770-11 || [[X1032BASE-3C-F]] || style="text-align:center;" | 2 ||  
|-
|-
| colspan="5" style="padding:0px" |  
| [[CECH-30xx]] || [[KTE-00x|KTE-001]] || 1-884-749-11 || [[X1032BASE-3C-F]] || style="text-align:center;" | 2 ||  
|-
|-
| [[CECH-43xx]] || [[RTX-001]] || || style="text-align:center;" | 2*32bits ||  
| [[CECH-40xx]] || [[MSX-00x|MSX-001]] || 1-886-928-11 || [[X1032BBBG-3C-F]] || style="text-align:center;" | 2 ||
|-
| [[CECH-40xx]] || [[MPX-00x|MPX-001]] || 1-887-233-11 || [[X1032BBBG-3C-F]] || style="text-align:center;" | 2 ||  
|-
|-
| [[CECH-43xx]] || [[REX-001]] || [[K4Y12324TE-KCB3]] || style="text-align:center;" | 2*32bits ||
|}
|}
<gallery>
File:Elpida XDR DRAM on production at June 4, 2013.jpg|Elpida XDR DRAM on production at June 4, 2013
File:Elpida XDR DRAM out of production at June 4, 2013.jpg|Elpida XDR DRAM out of production at June 4, 2013
</gallery>
=== Alternate table ===
=== Alternate table ===
{| border="1" cellspacing="0" cellpadding="5" border="#999" class="wikitable" style="border:1px solid #999; border-collapse: collapse;"  
{| border="1" cellspacing="0" cellpadding="5" border="#999" class="wikitable" style="border:1px solid #999; border-collapse: collapse;"  
Line 68: Line 64:
! Type !! Size !! Speed !! Voltage !! Packaging !! Manufact. !! Serial Number !! Amount !! Models
! Type !! Size !! Speed !! Voltage !! Packaging !! Manufact. !! Serial Number !! Amount !! Models
|-
|-
| Rambus&nbsp;XDR || 64MB || 400MHz || 1.8V+/-0.09V || FBGA-104 || Elpida || [[X5116ACSE-3C-E]] || 4x || [[CECHAxx]]/[[COK-00x#COK-001|COK-001]] up to including [[CECHGxx]]/[[SEM-00x|SEM-001]]
| Rambus&nbsp;XDR || 64MB || 400MHz || 1.8V+/-0.09V || FBGA-104 || Elpida || [[X5116AC-SE-3C-E]] || 4x || [[CECHAxx]]/[[COK-00x#COK-001|COK-001]] up to including [[CECHGxx]]/[[SEM-00x|SEM-001]]
|-
|-
| Rambus&nbsp;XDR || 64MB || 400MHz || 1.8V+/-0.09V || FBGA-104 || Samsung || [[K4Y50164UC-JCB3]] || 4x || ?Some initial models?
| Rambus&nbsp;XDR || 64MB || 400MHz || 1.8V+/-0.09V || FBGA-104 || Samsung || [[K4Y50164UC-JCB3]] || 4x || ?Some initial models?
Line 81: Line 77:
|-
|-
|}
|}
:


== Other XDR Rambus references ==
== Graphics Memory ==
* [https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/AF7832F379790768872572D10047E52B/$file/CellBE_HIG_65nm_v1.01_8Jun2007.pdf CellBE_HIG_65nm_v1.01_8Jun2007.pdf]
* [http://www.capsl.udel.edu/~jmanzano/Cell/docs/arch/BE_Hardwar_Init_Guide_v1.3_31March2006.pdf BE_Hardwar_Init_Guide_v1.3_31March2006.pdf]
* [http://www.rambus.com/assets/documents/products/dl_0362_v0_71.pdf Rambus XDR IO Cell (XIO) - dl_0362_v0_71.pdf]
* [http://www.rambus.com/assets/documents/products/dl_0161_v0_8.pdf XDR Architecture - Rambus dl_0161_v0_8.pdf]
* [http://www.rambus.com/assets/documents/products/xdr_dl_0476.pdf 8x4Mx16/8/4/2 - Rambus xdr_dl_0476.pdf]
* [http://www.rambus.com/assets/documents/products/dl_0169l_v0_81.pdf XDR Clock Generator - Rambus dl_0169l_v0_81.pdf]
* dl_0178_v0_93.pdf (january 2006)
* dl_0178_v0_95.pdf (august 2006)
 
* http://www.mirrorcreator.com/files/1KD96OYT/xdr_product_guide_mar_06_0.pdf_links
* http://www.mirrorcreator.com/files/1C1NTTYD/Elpida_E1819E20_0.pdf_links
* http://www.mirrorcreator.com/files/KGNOVWHK/Elpida_E0881E20_0.pdf_links
* http://www.mirrorcreator.com/files/SSF2GNEK/Samsung_k4y50xx4ue_rev10.pdf_links
* http://www.mirrorcreator.com/files/1FQRE8S5/Samsung_k4y50xx4uc_rev11_0.pdf_links
* http://www.mirrorcreator.com/files/11S5L1EW/Elpida_E1033E40_EOL_0.pdf_links


= Video Memory (VRAM) =
<div style="float:right">[[File:GDDR3 to RSX to CellBE diagram.png|200px|thumb|left|Quad 64MB GDDR3 (256MB total) to RSX to CellBE diagram ]]<br />[[File:RSX bare die.jpg|200px|thumb|left|RSX bare die<br />GPU in centre<br />4x GDDR3]]</div>
<div style="float:right">[[File:GDDR3 to RSX to CellBE diagram.png|x200px|thumb|right|Quad 64MB GDDR3 (256MB total) to RSX to CellBE diagram ]][[File:RSX_MEMORY.jpg|200px|thumb|left|RSX bare die<br />GPU in centre<br />4x GDDR3]]</div>


The 256MB of GDDR3 memory is located inside the [[RSX]] chip using four 64MB FBGA chips.
The 256MB of GDDR3 memory is located inside the [[RSX]] chip using four 64MB FBGA chips.
Line 109: Line 90:
| GDDR3 || 64MB (512Mbit) || 700MHz || 2.0V +/-0.1V || <strike>FBGA-136</strike> on-die || Samsung || [[K4J52324QC-SC14]] || 256MB total (4 chips) for PS3 Graphics Memory
| GDDR3 || 64MB (512Mbit) || 700MHz || 2.0V +/-0.1V || <strike>FBGA-136</strike> on-die || Samsung || [[K4J52324QC-SC14]] || 256MB total (4 chips) for PS3 Graphics Memory
|-
|-
| GDDR3 || 64MB (512Mbit) || 700MHz || 2.0V +/-0.1V || <strike>FBGA-136</strike> on-die || Infineon/Qimonda || [[HYB18H512322AF-14]] || 256MB total (4 chips) for PS3 Graphics Memory
| GDDR3 || 64MB (512Mbit) || 700MHz || 2.0V +/-0.1V || <strike>FBGA-136</strike> on-die || Qimonda || [[HYB18H512322AF-14]] || 256MB total (4 chips) for PS3 Graphics Memory (later models)
|-
| GDDR3 || 64MB (512Mbit) || ? || ? || ? || Samsung  || [[K4J52324KI-JC14]] || 256MB total (4 chips) for PS3 Graphics Memory
|-
| GDDR3 || 64MB (512Mbit) || ? || ? || ? || Samsung  || [[K4J52324KJ-JC14]] || 256MB total (4 chips) for PS3 Graphics Memory
|-
| GDDR3 || 128MB (1024Mbit) ? || ? || ? || ? || Hynix || [[H5RS5223DFA]] || 256MB total (2 chips ?) for PS3 Graphics Memory
|-
|-
|}
|}


= PS2 Compatibility Memory =
<div style="height:255px; overflow:auto"><!--// dirty and cheap spacer //--></div>
[https://en.wikipedia.org/wiki/RDRAM Rambus RDRAM]<br>
 
== Other XDR Rambus references ==
* [https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/AF7832F379790768872572D10047E52B/$file/CellBE_HIG_65nm_v1.01_8Jun2007.pdf CellBE_HIG_65nm_v1.01_8Jun2007.pdf]
* [http://www.capsl.udel.edu/~jmanzano/Cell/docs/arch/BE_Hardwar_Init_Guide_v1.3_31March2006.pdf BE_Hardwar_Init_Guide_v1.3_31March2006.pdf]
* [http://www.rambus.com/assets/documents/products/dl_0362_v0_71.pdf Rambus XDR IO Cell (XIO) - dl_0362_v0_71.pdf]
* [http://www.rambus.com/assets/documents/products/dl_0161_v0_8.pdf XDR Architecture - Rambus dl_0161_v0_8.pdf]
* [http://www.rambus.com/assets/documents/products/xdr_dl_0476.pdf 8x4Mx16/8/4/2 - Rambus xdr_dl_0476.pdf]
* [http://www.rambus.com/assets/documents/products/dl_0169l_v0_81.pdf XDR Clock Generator - Rambus dl_0169l_v0_81.pdf]
* dl_0178_v0_93.pdf (january 2006)
* dl_0178_v0_95.pdf (august 2006)
 
== PS2 Compatibility Memory ==
See: [[PS2 Compatibility]]
See: [[PS2 Compatibility]]


{{Motherboard Components}}<noinclude>[[Category:Main]]</noinclude>
{{Models}}
 
[[Category:RAM]]
Please note that all contributions to PS3 Developer wiki are considered to be released under the GNU Free Documentation License 1.2 (see PS3 Developer wiki:Copyrights for details). If you do not want your writing to be edited mercilessly and redistributed at will, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource. Do not submit copyrighted work without permission!

To protect the wiki against automated edit spam, we kindly ask you to solve the following hCaptcha:

Cancel Editing help (opens in new window)

Templates used on this page:

Retrieved from "http://www.psdevwiki.com/ps3/RAM"