Editing PS2 Emulation/PS2 Config Commands

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  0x4000000  = Enable type 2 config from cmd 0x12.
  0x4000000  = Enable type 2 config from cmd 0x12.
  0x8000000  = Accurate VU0 DIV opcode, not used in COP2 mode.
  0x8000000  = Accurate VU0 DIV opcode, not used in COP2 mode.
  0x10000000 = Full Accurate VU0 MUL. Use runtime from CMD 0x10, but for every matching VU0 opcode, including opcodes like MSUB for mul part.
  0x10000000 = Fast Accurate VU0 MUL. Try to round mantissa. Opcodes like MSUB/MADD additionally require 0x100000 to be enabled, otherwise command skip them. Not used in COP2 mode.
0x20000000 = Full Accurate VU0 MUL. Use runtime from CMD 0x10, but for every matching VU0 opcode, including opcodes like MSUB for mul part.
               Opcodes like MSUB/MADD additionally require 0x100000 to be enabled, otherwise command skip them.
               Opcodes like MSUB/MADD additionally require 0x100000 to be enabled, otherwise command skip them.
0x20000000 = Fast Accurate VU0 MUL. Opcodes like MSUB/MADD additionally require 0x100000 to be enabled, otherwise command skip them. Not used in COP2 mode.
   
   
  Selecting both 0x10000000 and 0x20000000 (0x30000000) work the same way as 0x20000000.
  Selecting both 0x10000000 and 0x20000000 (0x30000000) work the same way as 0x20000000.
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{{Boxcomm|id=0x20|name=Unknown|data=1x uint64_t}}
{{Boxcomm|id=0x20|name=Unknown|data=1x uint64_t}}
Default 0x3C
Default 0x3C
  Config value is used as multiplier for value:
  Config value is used as multiplier for some value, and result is used in vsync related runtimes.
  if (mode == NTSC) multiplicand = 2535;
  Is worth to note that 0x3C is default multiplier even for PAL titles, so is not stricly related to framerate,
if (mode == PAL)  multiplicand = 5107;
  but to vsync counters (where 0x3C is still wrong anyway..). Result of multiply is also compared at some point to vsync delay value.  
  if (mode == 1080) multiplicand = 2364;
At default config value of 0x3C results are:
NTSC = 152100
PAL  = 306420
1080 = 141840
Result is compared against decrementer ticks.
This result value determines how frequently emulator events test checks GS related things.
This include raising GS irq if VSINT/SIGNAL/FINISH occurred, updating display parameters, etc.
 
*Valid values found: 10d, 60d, 100d, 120d, 200d, 240d
*Valid values found: 10d, 60d, 100d, 120d, 200d, 240d


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=PS2 Gxemu Commands=
=PS2 Gxemu Commands=
PS2 GX Emu commands are Big Endian unless noted. Every command size is 0x18, and unused data need to be filled with zeros. Commands which point to emulator memory have additional data, but command itself is still 0x18 in size. Data fields are just example values and can be changed to different value when needed.
PS2 GX Emu commands are Big Endian unless noted. Every command size is 0x18, and unused data need to be filled with zeros. Commands which point to emulator memory have additional data, but command itself is still 0x18 in size. Data fields are just example values and can be changed to different value when needed.  
{{BoxcommGX|id=0x00|net_id=0x01|data=FIXME|}}
Inject precompiled function on selected EE offset.
Format:
32 bit ID  | 32 bit align | 32 bit EE offset | 32 bit align | 64bit ptr to emu memory
0x00000000 |  0x00000000  |    0x0012345C    |  0x00000000  |  0x00000000000366C4
<div class="mw-collapsible mw-collapsed" data-expandtext="{{int:Show}}" data-collapsetext="{{int:Hide}}" style="width:1000px; background:#cccccc;">'''More info'''
<div class="mw-collapsible-content" style="text-align:left;">
Netemu sub ID to gxemu pointer:
0x00 = 0x36B40
0x01 = 0x35FB0
0x02 = 0x34068
0x03 = 0x34144
0x04 = 0x33F98
0x05 = 0x36CF8
0x06 = 0x34224
0x07 = 0x37850
0x08 = 0x33DFC
0x09 = 0x36C04
0x0A = 0x36EF0
0x0B = 0x34354
0x0C = 0x34424
0x0D = 0x34520
0x0E = 0x345FC
0x0F = 0x365F0
0x10 = 0x36510
0x11 = 0x36430
0x12 = 0x34DD0
0x13 = 0x366C4
0x14 = 0x34EDC
0x15 = 0x3795C
0x16 = 0x3521C
0x17 = 0x347D0
0x18 = 0x35300
0x19 = 0x36E28
0x1A = 0x37614
0x1B = 0x35434
0x1C = 0x354F8
0x1D = 0x355BC
0x1E = 0x35680
0x1F = 0x35744
0x20 = 0x35808
0x21 = 0x358CC
0x22 = 0x35990
0x23 = 0x35A54
0x24 = 0x35B18
0x25 = 0x35BDC
0x26 = 0x35CA0
0x27 = 0x35D64
0x28 = 0x35E28
0x29 = 0x35EEC
0x2A = 0x35158
0x2B = 0x34994
0x2C = 0x36FC8
0x2D = 0x3607C
0x2F = 0x34A70
0x30 = 0x34B48
0x31 = 0x34C20
0x32 = 0x34CF8
0x33 = 0x37714
ID >= 0x34 unsupported
Offsets for 4.75+ gx emulator
</div>
</div>
{{BoxcommGX|id=0x01|net_id=0x02|data=1x int32|}}
{{BoxcommGX|id=0x01|net_id=0x02|data=1x int32|}}
Used in function that handle D6 CHCR writes (SIF1), seems to be some kind of timing command for EE --> IOP DMA.
Used in function that handle D6 CHCR writes (SIF1), seems to be some kind of timing command for EE --> IOP DMA.
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  if readVu1Code(i) & 0x80000000FFFFFFFF == 0x0000000040000001
  if readVu1Code(i) & 0x80000000FFFFFFFF == 0x0000000040000001
     writeVu1Code(i, 0x000000008000033C & 0x00000000FFFFFFFF)
     writeVu1Code(i, 0x000000008000033C & 0x00000000FFFFFFFF)
{{BoxcommGX|id=0x08|net_id=0x09|data=1x int32|}}
Patch 2 x 32 bit opcodes of EE executable code.
Format:
32 bit ID  | 32 bit align | 64bit ptr to emu memory | 32 bit count | 32 bit align
0x00000008 |  0x00000000  |  0x0000000000341190    |  0x00000002  |  0x00000000
Additional example data at 0x341190 looks like this:
  32 bit EE offset  | 32 bit align | 32 bit original opcode | 32 bit original opcode | 32 bit replace opcode | 32 bit replace opcode
    0x00418750    |  0x00000000  |      0x1062FFFA      |      0x00000000      |      0x00000000      |      0x00000000
due to patch count == 2 in this example, there is next set of data right after first one:
  32 bit EE offset  | 32 bit align | 32 bit original opcode | 32 bit original opcode | 32 bit replace opcode | 32 bit replace opcode
    0x00418808    |  0x00000000  |      0x1062FFFA      |      0x00000000      |      0x00000000      |      0x00000000
<div class="mw-collapsible mw-collapsed" data-expandtext="{{int:Show}}" data-collapsetext="{{int:Hide}}" style="width:1000px; background:#cccccc;">'''More info'''
<div class="mw-collapsible-content" style="text-align:left;">
This command read and write opcodes as a 64 bit value. This can be really confusing when creating custom config.
Lets assume that EE offset 0x100000 holds value (in raw hex) 00 11 22 33 44 55 66 77 and we want to change it to 88 99 AA BB CC DD EE FF
Format:
32 bit ID  | 32 bit align | 64bit ptr to emu memory | 32 bit count | 32 bit align
0x00000008 |  0x00000000  |  0x0000000000341190    |  0x00000001  |  0x00000000
Additional example data at 0x341190 looks like this:
  32 bit EE offset  | 32 bit align | 32 bit original opcode | 32 bit original opcode | 32 bit replace opcode | 32 bit replace opcode
    0x00100000    |  0x00000000  |      0x77665544      |      0x33221100      |      0xFFEEDDCC      |      0xBBAA9988
                    |              |value read from 0x100004|value read from 0x100000|value write to 0x100004|value write to 0x100000
This happen because emulator read 64 bit value from 0x100000 and reverse it from little to big endian as whole 64 bits. Exactly the same happen for values that emulator write to memory.
This little code snippet can help little bit with conversion.
# Value to convert, copied from hex editor or disassembler.
x = "00 11 22 33 44 55 66 77"
x = x.replace(" ", "")
x = int(x, 16)
x = (x & 0x00000000FFFFFFFF) << 32 | (x & 0xFFFFFFFF00000000) >> 32
x = (x & 0x0000FFFF0000FFFF) << 16 | (x & 0xFFFF0000FFFF0000) >> 16
x = (x & 0x00FF00FF00FF00FF) << 8  | (x & 0xFF00FF00FF00FF00) >> 8
a = x >> 56
b = (x >> 48) & 0xFF
c = (x >> 40) & 0xFF
d = (x >> 32) & 0xFF
e = (x >> 24) & 0xFF
f = (x >> 16) & 0xFF
g = (x >> 8) & 0xFF
h = x & 0xFF
print("{:02X} {:02X} {:02X} {:02X} {:02X} {:02X} {:02X} {:02X}".format(a,b,c,d,e,f,g,h))
Beside own python installation, code can be used on site like https://www.w3schools.com/python/trypython.asp?filename=demo_compiler
</div>
</div>
{{BoxcommGX|id=0x09|net_id=0x0B|data=1x int32|}}
Patch disc data during read operation. <!--todo: explain lba/offset.. offset.-->
Format:
32 bit ID  | 32 bit align | 64bit ptr to emu memory | 32 bit count | 32 bit align
0x00000009 |  0x00000000  |  0x0000000000341190    |  0x00000001  |  0x00000000
Additional example data at 0x341190 looks like this:
  32 bit lba | 32 bit offset in lba | 64 bit ptr to replace data | 64 bit ptr to original data | 32 bit data size in bytes | 32 bit align
  0x00000471 |      0x00000280      |    0x00000000003411B0    |    0x00000000003411B4      |        0x00000004        |  0x00000000


{{BoxcommGX|id=0x0A|net_id=0x0C|data=2x uint16|}}
{{BoxcommGX|id=0x0A|net_id=0x0C|data=2x uint16|}}
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  32 bit ID  | 32 bit align | 32 bit align | 32 bit align | 32 bit align | 32 bit align
  32 bit ID  | 32 bit align | 32 bit align | 32 bit align | 32 bit align | 32 bit align
  0x00000019 |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000
  0x00000019 |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000
<div class="mw-collapsible mw-collapsed" data-expandtext="{{int:Show}}" data-collapsetext="{{int:Hide}}" style="width:700px; background:#cccccc;">'''More info'''
<div class="mw-collapsible-content" style="text-align:left;">
Command disable reads/writes to selected IOP HW registers. Disabled regs are:
* 0x10000000 - 0x10003FFF (DEV9/SPEED/ATA/SMAP)
* 0x1F801460 - 0x1F80147F (Unknown)
Command is auto applied to titles listed here (duplicates are really there in emu too):
    Hash          ID                Name
0x0CD1298155  SLES_540.13  World Snooker Championship 2007
0x12C93199A5  SLES_518.40  NHL Hitz Pro
0x15C93199AD  SLES_549.13  Pro Evolution Soccer 2008
0x24D92589A5  SLUS_211.86  NBA Ballers - Phenom
0x2CD12D8125  SLUS_212.35  MLB 2K6
0x34C9359935  SLUS_211.38  X-Men Legends II - Rise of Apocalypse
0x34C93599E5  SLUS_211.28  Blitz - The League
0x34C93599E5  SLUS_211.28  Blitz - The League
0x449961C9E5  SLES_542.10  NBA 2K7
0x4C9169C1CD  SLES_542.46  FIFA '07
0x4C9169C1D5  SLES_542.45  NHL '07
0x4C9169C1DD  SLES_542.44  FIFA '07
0x4C9169C1E5  SLES_542.43  FIFA '07
0x4C9169C1F5  SLES_542.41  FIFA '07
0x4C9169C1FD  SLES_542.40  FIFA '07
0x4CB14DE12D  SLUS_213.74  Marvel - Ultimate Alliance
0x54A955F915  SLUS_212.74  Outrun 2006 - Coast 2 Coas
0x5CA15DF165  SLUS_213.01  World Series of Poker
0x5CA15DF1FD  SLUS_212.86  WWE SmackDown! vs RAW 2006
0x5CA15DF1FD  SLUS_212.86  WWE SmackDown! vs RAW 2006
0x649965C94D  SLUS_214.63  Tom Clancy's Ghost Recon 2
0x649965C955  SLUS_214.60  NBA Live '07
0x649965C95D  SLUS_214.61  NASCAR '07
0x649965C965  SLUS_214.58  NHL '07
0x649965C96D  SLUS_214.59  NCAA Football '07
0x6BB149E15D  SLES_531.04  Tom Clancy's Rainbow Six - Lockdown
0x6C916DC165  SLUS_214.91  World Series of Poker - Tournament of Champions
0x6C916DC1A5  SLUS_214.83  Tiger Woods PGA Tour '07
0x6C916DC1AD  SLUS_214.82  NFL Street 3
0x6C916DC1B5  SLUS_214.81  NCAA March Madness '07
0x6C916DC1D5  SLUS_214.77  Madden NFL '07 [Hall of Fame Edition]
0x6C916DC1DD  SLUS_214.76  Madden NFL '07
0x748975D9DD  SLUS_213.83  Fight Night - Round 3
0x7C817DD125  SLUS_214.33  FIFA Soccer '07
0x7C817DD165  SLUS_214.25  NHL 2K7
0x7C817DD16D  SLUS_214.24  NBA 2K7
0x7C817DD175  SLUS_214.27  WWE SmackDown! vs RAW 2007
0x7C817DD1CD  SLUS_214.12  World Championship Poker featuring Howard Lederer - All-In
0x84798529BD  SLUS_205.65  Champions of Norrath
0x8559A109AD  uuunnnnnkkk 
0x8579852915  SLUS_215.68  Arena Football - Road to Glory
0x8579852965  SLUS_215.82  MVP '07 - NCAA Baseball
0x8D51A90145  SLES_545.11  UEFA Champions League
0x8D51A901B5  SLES_545.13  UEFA Champions League
0x8D51A901BD  SLES_545.12  UEFA Champions League
0x8D718D21BD  SLUS_216.20  NCAA Football '08
0x9C619D31E5  SLUS_205.41  NBA Ballers
0x9D41B911AD  SLES_544.48  World Series of Poker - Tournament of Champions
0x9D619D31C5  SLUS_215.61  Major League Baseball 2K7
0x9F29357805  SCUS_975.44  NBA '07 featuring The Life Vol.2
0x9F293578E5  SCUS_975.56  MLB '07 - The Show
0xB549B51915  SLUS_216.38  Madden NFL '0
0xB549B51925  SLUS_216.32  NHL 2K8
0xB549B5195D  SLUS_216.47  NHL '08
0xB549B519A5  SLUS_216.48  FIFA Soccer '08
0xB549B519AD  SLUS_216.49  NBA Live '08
0xBC61793025  SCES_532.85  Ratchet - Gladiator
0xBD41BD1105  SLUS_216.69  NBA 2K8
0xC439C569F5  SLUS_208.20  Tom Clancy's Ghost Recon - Jungle Storm
0xC7716D20D5  SCUS_974.01  Hot Shots Golf FORE!
0xC7716D20D5  SCUS_974.01  Hot Shots Golf FORE!
0xCA11E941F5  SLES_516.97  SSX 3
0xCF7965285D  SCUS_973.53  Ratchet and Clank - Up Your Arsenal
0xCF7965285D  SCUS_973.53  Ratchet and Clank - Up Your Arsenal
0xD20911582D  SCES_515.93  Hardware Online Arena [Beta, Promo & Full Release]
0xD7617D308D  SCUS_973.28  Gran Turismo 4
0xE339C1695D  SLES_525.45  Star Wars Battlefront
0xE794CCB06D  PCPX_980.42  Minna no Tennis
0xEA3129608D  SCES_515.78  Network Access Disc [Original, v4.02 & v4.03]
0xEC11ED4115  SLUS_209.73  Champions - Return to Arms
0xEF594508D5  SCUS_975.00  MLB '06 - The Show
0xF409F559AD  SLUS_208.89  MLB Slugfest - Loaded
0xF7415D10E5  SCUS_974.65  Ratchet - Deadlocked
0xF7415D10E5  SCUS_974.65  Ratchet - Deadlocked
As a result config disable HDD/NET capabilities.
</div>
</div>
{{BoxcommGX|id=0x1A|net_id=0x1D|data=1x int8|}}
Sets multitap to specific controller ports and adjusts the order of ports to which controllers are synced. Default 3
*0 = no multitap set (only when needed). Controller sync order: 1/1-A, 2/2-A, 1-B, 2-B...
*1 = sets multitap in controller port 1 at all times. Controller sync order: 1/1-A, 1-B, 1-C, 1-D...
*2 = sets multitap in controller port 2 at all times. Controller sync order: 1/1-A, 2/2-A, 2-B, 2-C...
*3 = sets multitaps in both controller ports at all times. Controller sync order: same as 0
Format:
32 bit ID  | 32 bit align | 8 bit data | 24 bit align | 32 bit align | 32 bit align | 32 bit align
0x0000001A |  0x00000000  |    0x01    |  0x000000  |  0x00000000  |  0x00000000  |  0x00000000
{{BoxcommGX|id=0x1B|net_id=0x1E|data=1x int8|}}
Unknown. Probably mtap related. Command is a 2 bit bitfield. Default value 0
Format:
32 bit ID  | 32 bit align | 8 bit data | 24 bit align | 32 bit align | 32 bit align | 32 bit align
0x0000001B |  0x00000000  |    0x01    |  0x000000  |  0x00000000  |  0x00000000  |  0x00000000
{{BoxcommGX|id=0x1C|net_id=0x1F|data=1x int32|}}
Make VIF0 commands MSCAL/MSCALF/MSCNT/MPG/FLUSHE non instant.<br>By default every VIF0 command take 1 cycle, so it's instant.
This config give vif0 some timing sense. Value is cycle count before first event check related to VIF0.<br>
When delta from config passed and vif0 is still running, add 500 cycles and go on until next event test.<br>
This can also be used to ensure that next vif0 command after MSCAL/MSCALF/MSCNT/MPG/FLUSHE won't run until delta from config passed.
Format:
32 bit ID  | 32 bit align | 32 bit data | 32 bit align | 32 bit align | 32 bit align
0x0000001C |  0x00000000  | 0x000003F8  |  0x00000000  |  0x00000000  |  0x00000000
{{BoxcommGX|id=0x1D|net_id=0x20|data=1x int64|}}
Vblank timing related, still partially unknown.
Format:
32 bit ID  | 32 bit align |    64 bit data    | 32 bit align | 32 bit align
0x0000001D |  0x00000000  | 0x00000000000000C8 |  0x00000000  |  0x00000000
{{BoxcommGX|id=0x1E|net_id=0x21|data=1x int32|}}
Option one default value = 1, when set to 0: r5900 CACHE opcode IXLTG store 0 in COP0 TagLo register. More than that recompiler skip function responsible for analyze and emitting costly iCache checks.<br>
This drastically reduce emitted code size, and practically disable iCache emulation. Additionally CACHE IXIN/IHIN opcodes use different very long code path (this can be skipped with cmd 0x03).<br>
Option two default value = 0, when set to 1: Emit some kind of check for current r5900 PC with possible trap opcode at the end. 1 is valid only when option one is 0.
*0 = sets an option one to 0 and option two to 0
*1 = sets an option one to 0 and option two to 1
*2 = sets an option one to 1 and option two to 0 (default)
Format:
32 bit ID  | 32 bit align | 32 bit data | 32 bit align | 32 bit align | 32 bit align
0x0000001E |  0x00000000  | 0x00000002  |  0x00000000  |  0x00000000  |  0x00000000
{{BoxcommGX|id=0x1F|net_id=0x23|data=None|}}
Patch spe 4 program with new custom VIF1 STCYCL alike command 08h handler.
This command is useful only with additional 0x00 hooks. Said hooks inject 08h VIF1 command into game code when other conditions are met.
Format:
32 bit ID  | 32 bit align | 32 bit align | 32 bit align | 32 bit align | 32 bit align
0x0000001F |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000
{{BoxcommGX|id=0x20|net_id=0x24|data=1x int64|}}
SIO2 timing related, still partially unknown.
Format:
32 bit ID  | 32 bit align |    64 bit data    | 32 bit align | 32 bit align
0x00000020 |  0x00000000  | 0x0000000000002EE0 |  0x00000000  |  0x00000000
{{BoxcommGX|id=0x21|net_id=Not available|data=1x int32|}}
Unknown, GSGIF SPE related.
Format:
32 bit ID  | 32 bit align | 32 bit data | 32 bit align | 32 bit align | 32 bit align
0x00000021 |  0x00000000  | 0x00000009  |  0x00000000  |  0x00000000  |  0x00000000
{{BoxcommGX|id=0x22|net_id=0x26|data=2x int32|}}
Improves FPU accuracy for selected memory range. Efective only on: ADD.s, SUB.s, ADDA.s, SUBA.s, MADD.s, MSUB.s, MADDA.s, MSUBA.s.
For M(UL) opcodes, command is active only on ADD/SUB stage.
Format:
32 bit ID  | 32 bit align | 32 bit EE start memory offset | 32bit EE end memory offset | 32 bit align | 32 bit align
0x00000022 |  0x00000000  |          0x0012A3D4          |        0x0012A468        |  0x00000000  |  0x00000000
{{BoxcommGX|id=0x23|net_id=0x27|data=2x int32|}}
Improves COP2 operations accuracy for selected memory range. Effective only for opcodes:
VSUBAxyzw, VSUBAq, VSUBAi, VSUBA, VSUBxyzw, VSUBq, VSUBi, VSUB, VMSUBAxyzw,
VMSUBAq, VMSUBAi, VMSUBA, VMSUBxyzw, VMSUBq, VMSUBi, VMSUB, VMADDAxyzw,
VMADDAq, VMADDAi, VMADDA, VMADDxyzw, VMADDq, VMADDi, VMADD, VADDAxyzw,
VADDAq, VADDAi, VADDA, VADDxyzw, VADDq, VADDi, VADD
Format:
32 bit ID  | 32 bit align | 32 bit EE start memory offset | 32bit EE end memory offset | 32 bit align | 32 bit align
0x00000023 |  0x00000000  |          0x0012A3D4          |        0x0012A468        |  0x00000000  |  0x00000000
{{BoxcommGX|id=0x24|net_id=0x28|data=1x int32|}}
Unknown, CDVD related. Only accept values 0/1/2/3
Format:
32 bit ID  | 32 bit align | 32 bit data | 32 bit align | 32 bit align | 32 bit align
0x00000024 |  0x00000000  | 0x00000001  |  0x00000000  |  0x00000000  |  0x00000000
{{BoxcommGX|id=0x25|net_id=0x29|data=2x int32|}}
Seek time modifier. Exact values meaning is unknown for now, they are used as multiplier. First param affect fast seek time, second param affect full seek time. Default value is 0x1F40, 0xBB80 (8000, 48000). Config affect only CDVD N Command Seek, read command that "SeekToSector" is not affected.
Format:
32 bit ID  | 32 bit align | 32 bit data | 32 bit data | 32 bit align | 32 bit align
0x00000025 |  0x00000000  | 0x00001F40  |  0x0000BB80 |  0x00000000  |  0x00000000
{{BoxcommGX|id=0x26|net_id=0x2A|data=None|}}
Unknown, used only in All-Star Baseball 2004
Format:
32 bit ID  | 32 bit align | 32 bit align | 32 bit align | 32 bit align | 32 bit align
0x00000026 |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000
{{BoxcommGX|id=0x27|net_id=0x2B|data=None|}}
When enabled emulated register 0x1F40200F (disc type) is set to 0x13 (PS2CDDA) when media type detected by emu is 0x12 (PS2CD). Required for multi-track PS2 games like Dance Factory.
Format:
32 bit ID  | 32 bit align | 32 bit align | 32 bit align | 32 bit align | 32 bit align
0x00000027 |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000
{{BoxcommGX|id=0x28|net_id=0x2C|data=1x int32|}}
Store (value | value << 32 | value << 64 | value << 96) in SPE 0 (IOP) LS.
Format:
32 bit ID  | 32 bit align | 32 bit data | 32 bit align | 32 bit align | 32 bit align
0x00000028 |  0x00000000  | 0x00000001  |  0x00000000  |  0x00000000  |  0x00000000
{{BoxcommGX|id=0x29|net_id=Not available|data=None|}}
Skip one of functions in r5900 event test. Said function interact with GSGIF SPE and GS hardware, but in some conditions can also write to BGCOLOR GS register (why?).
Used in Final Fantasy X
Format:
32 bit ID  | 32 bit align | 32 bit align | 32 bit align | 32 bit align | 32 bit align
0x00000029 |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000
{{BoxcommGX|id=0x2A|net_id=0x2E|data=1x int32|}}
Unknown.
Format:
32 bit ID  | 32 bit align | 32 bit data | 32 bit align | 32 bit align | 32 bit align
0x0000002A |  0x00000000  | 0x00000172  |  0x00000000  |  0x00000000  |  0x00000000
{{BoxcommGX|id=0x2B|net_id=0x2F|data=1x int32|}}
Store value in SPE 1 (PS2 SPU2) LS. Used values are 1, and 2 (after andi, so 3 trigger both configs).
Indigo Prophecy/Fahrenheit uses 0x1, Kengo 3 uses 0x2
Format:
32 bit ID  | 32 bit align | 32 bit data | 32 bit align | 32 bit align | 32 bit align
0x0000002B |  0x00000000  | 0x00000001  |  0x00000000  |  0x00000000  |  0x00000000
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