Editing PS2 Emulation/PS2 Config Commands
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=PS2 Netemu Commands= | ==PS2 Netemu Commands== | ||
<!-- We need to find a better way to organize the commands info below, right now all the info is "constricted" inside the same table but is better to take them out of the table to have more freedon when adding comments, etc... Are a lot so by now i prefer to dont make page sections for every command. Im going to try something that visually looks like page sections but are not (so are not going to be displayed in the TOC at top of the page). With this change we are moving forward because the command info is not going to be inside the same table anymore, im going to split them but the visual look and other details are not going to be definitive because later can be converted into page sections if someone insists in it --> | <!-- We need to find a better way to organize the commands info below, right now all the info is "constricted" inside the same table but is better to take them out of the table to have more freedon when adding comments, etc... Are a lot so by now i prefer to dont make page sections for every command. Im going to try something that visually looks like page sections but are not (so are not going to be displayed in the TOC at top of the page). With this change we are moving forward because the command info is not going to be inside the same table anymore, im going to split them but the visual look and other details are not going to be definitive because later can be converted into page sections if someone insists in it --> | ||
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0x4000000 = Enable type 2 config from cmd 0x12. | 0x4000000 = Enable type 2 config from cmd 0x12. | ||
0x8000000 = Accurate VU0 DIV opcode, not used in COP2 mode. | 0x8000000 = Accurate VU0 DIV opcode, not used in COP2 mode. | ||
0x10000000 = Full Accurate VU0 MUL. Use runtime from CMD 0x10, but for every matching VU0 opcode, including opcodes like MSUB for mul part. | 0x10000000 = Fast Accurate VU0 MUL. Try to round mantissa. Opcodes like MSUB/MADD additionally require 0x100000 to be enabled, otherwise command skip them. Not used in COP2 mode. | ||
0x20000000 = Full Accurate VU0 MUL. Use runtime from CMD 0x10, but for every matching VU0 opcode, including opcodes like MSUB for mul part. | |||
Opcodes like MSUB/MADD additionally require 0x100000 to be enabled, otherwise command skip them. | Opcodes like MSUB/MADD additionally require 0x100000 to be enabled, otherwise command skip them. | ||
Selecting both 0x10000000 and 0x20000000 (0x30000000) work the same way as 0x20000000. | Selecting both 0x10000000 and 0x20000000 (0x30000000) work the same way as 0x20000000. | ||
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{{Boxcomm|id=0x20|name=Unknown|data=1x uint64_t}} | {{Boxcomm|id=0x20|name=Unknown|data=1x uint64_t}} | ||
Default 0x3C | Default 0x3C | ||
Config value is used as multiplier for value | Config value is used as multiplier for some value, and result is used in vsync related runtimes. | ||
Is worth to note that 0x3C is default multiplier even for PAL titles, so is not stricly related to framerate, | |||
but to vsync counters (where 0x3C is still wrong anyway..). Result of multiply is also compared at some point to vsync delay value. | |||
*Valid values found: 10d, 60d, 100d, 120d, 200d, 240d | *Valid values found: 10d, 60d, 100d, 120d, 200d, 240d | ||
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{{Boxcomm|id=0x50|name=Enable pressure sensitive controls|data=N/A}} | {{Boxcomm|id=0x50|name=Enable pressure sensitive controls|data=N/A}} | ||
=PS2 Gxemu Commands= | ==PS2 Gxemu Commands== | ||
PS2 GX Emu commands are Big Endian unless noted. Every command size is 0x18, and unused data need to be filled with zeros | PS2 GX Emu commands are Big Endian unless noted. Every command size is 0x18, and unused data need to be filled with zeros. | ||
{{ | {{Boxcomm|id=0x01|name=Unknown|data=1x int32|}} | ||
Used in function that handle D6 CHCR writes (SIF1), seems to be some kind of timing command for EE --> IOP DMA. | Used in function that handle D6 CHCR writes (SIF1), seems to be some kind of timing command for EE --> IOP DMA. | ||
Format: | Format: | ||
32 bit ID | 32 bit align | | 32 bit ID | 32 bit align | 32bit data | 32 bit align | 32 bit align | 32 bit align | ||
0x00000001 | 0x00000000 | 0x00000BB8 | 0x00000001 | 0x00000000 | 0x00000BB8 | 0x00000000 | 0x00000000 | 0x00000000 | ||
{{ | {{Boxcomm|id=0x02|name=Unknown|data=None|}} | ||
Skip r5900 CACHE IXIN/IHIN (Index/Hit invalidate) opcodes. | Skip r5900 CACHE IXIN/IHIN (Index/Hit invalidate) opcodes. | ||
Format: | Format: | ||
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0x00000002 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000002 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | ||
{{ | {{Boxcomm|id=0x03|name=Unknown|data=1x int32|}} | ||
Patch SPE 4 program (eedma) by searching for ila r4, xxxxx, starting at 0x178A0 and replacing them with (0x42000004 | ((value << 7) & 0x1FFFF80) 0x42000004 is ila r4 opcode. Due to opcode encoding example result of that patch with value 0x08 will be 0x42000404 (ila r4, 0x08). There is little bit more than that, but main purpose is just to patch SPE program behavior. | Patch SPE 4 program (eedma) by searching for ila r4, xxxxx, starting at 0x178A0 and replacing them with (0x42000004 | ((value << 7) & 0x1FFFF80) 0x42000004 is ila r4 opcode. Due to opcode encoding example result of that patch with value 0x08 will be 0x42000404 (ila r4, 0x08). There is little bit more than that, but main purpose is just to patch SPE program behavior. | ||
Format: | Format: | ||
32 bit ID | 32 bit align | | 32 bit ID | 32 bit align | 32bit data | 32 bit align | 32 bit align | 32 bit align | ||
0x00000003 | 0x00000000 | 0x00000008 | 0x00000003 | 0x00000000 | 0x00000008 | 0x00000000 | 0x00000000 | 0x00000000 | ||
{{ | {{Boxcomm|id=0x04|name=Unknown|data=None|}} | ||
Patch spe 4 program to use alternative VIF1 Direct/DirectHL command handler. | Patch spe 4 program to use alternative VIF1 Direct/DirectHL command handler. | ||
Format: | Format: | ||
32 bit ID | 32 bit align | 32 bit align | 32 bit align | 32 bit align | 32 bit align | 32 bit ID | 32 bit align | 32 bit align | 32 bit align | 32 bit align | 32 bit align | ||
0x00000004 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000004 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | ||