Editing PS2 Emulation/PS2 Config Commands
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Latest revision | Your text | ||
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0x4000000 = Enable type 2 config from cmd 0x12. | 0x4000000 = Enable type 2 config from cmd 0x12. | ||
0x8000000 = Accurate VU0 DIV opcode, not used in COP2 mode. | 0x8000000 = Accurate VU0 DIV opcode, not used in COP2 mode. | ||
0x10000000 = Full Accurate VU0 MUL. Use runtime from CMD 0x10, but for every matching VU0 opcode, including opcodes like MSUB for mul part. | 0x10000000 = Fast Accurate VU0 MUL. Try to round mantissa. Opcodes like MSUB/MADD additionally require 0x100000 to be enabled, otherwise command skip them. Not used in COP2 mode. | ||
0x20000000 = Full Accurate VU0 MUL. Use runtime from CMD 0x10, but for every matching VU0 opcode, including opcodes like MSUB for mul part. | |||
Opcodes like MSUB/MADD additionally require 0x100000 to be enabled, otherwise command skip them. | Opcodes like MSUB/MADD additionally require 0x100000 to be enabled, otherwise command skip them. | ||
Selecting both 0x10000000 and 0x20000000 (0x30000000) work the same way as 0x20000000. | Selecting both 0x10000000 and 0x20000000 (0x30000000) work the same way as 0x20000000. | ||
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=PS2 Gxemu Commands= | =PS2 Gxemu Commands= | ||
PS2 GX Emu commands are Big Endian unless noted. Every command size is 0x18, and unused data need to be filled with zeros. Commands which point to emulator memory have additional data, but command itself is still 0x18 in size. Data fields are just example values and can be changed to different value when needed. | PS2 GX Emu commands are Big Endian unless noted. Every command size is 0x18, and unused data need to be filled with zeros. Commands which point to emulator memory have additional data, but command itself is still 0x18 in size. Data fields are just example values and can be changed to different value when needed. | ||
{{ | {{Boxcomm|id=0x01|name=Unknown|data=1x int32|}} | ||
Used in function that handle D6 CHCR writes (SIF1), seems to be some kind of timing command for EE --> IOP DMA. | Used in function that handle D6 CHCR writes (SIF1), seems to be some kind of timing command for EE --> IOP DMA. | ||
Format: | Format: | ||
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0x00000001 | 0x00000000 | 0x00000BB8 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000001 | 0x00000000 | 0x00000BB8 | 0x00000000 | 0x00000000 | 0x00000000 | ||
{{ | {{Boxcomm|id=0x02|name=Unknown|data=None|}} | ||
Skip r5900 CACHE IXIN/IHIN (Index/Hit invalidate) opcodes. | Skip r5900 CACHE IXIN/IHIN (Index/Hit invalidate) opcodes. | ||
Format: | Format: | ||
Line 755: | Line 755: | ||
0x00000002 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000002 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | ||
{{ | {{Boxcomm|id=0x03|name=Unknown|data=1x int32|}} | ||
Patch SPE 4 program (eedma) by searching for ila r4, xxxxx, starting at 0x178A0 and replacing them with (0x42000004 | ((value << 7) & 0x1FFFF80) 0x42000004 is ila r4 opcode. Due to opcode encoding example result of that patch with value 0x08 will be 0x42000404 (ila r4, 0x08). There is little bit more than that, but main purpose is just to patch SPE program behavior. | Patch SPE 4 program (eedma) by searching for ila r4, xxxxx, starting at 0x178A0 and replacing them with (0x42000004 | ((value << 7) & 0x1FFFF80) 0x42000004 is ila r4 opcode. Due to opcode encoding example result of that patch with value 0x08 will be 0x42000404 (ila r4, 0x08). There is little bit more than that, but main purpose is just to patch SPE program behavior. | ||
Format: | Format: | ||
Line 761: | Line 761: | ||
0x00000003 | 0x00000000 | 0x00000008 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000003 | 0x00000000 | 0x00000008 | 0x00000000 | 0x00000000 | 0x00000000 | ||
{{ | {{Boxcomm|id=0x04|name=Unknown|data=None|}} | ||
Patch spe 4 program to use alternative VIF1 Direct/DirectHL command handler. | Patch spe 4 program to use alternative VIF1 Direct/DirectHL command handler. | ||
Format: | Format: | ||
Line 767: | Line 767: | ||
0x00000004 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000004 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | ||
{{ | {{Boxcomm|id=0x05|name=Unknown|data=None|}} | ||
Patch spe 4 program to use alternative VIF1 Offset command handler. | Patch spe 4 program to use alternative VIF1 Offset command handler. | ||
Format: | Format: | ||
Line 773: | Line 773: | ||
0x00000005 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000005 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | ||
{{ | {{Boxcomm|id=0x06|name=Unknown|data=1x int32|}} | ||
Delay XGKICK by x cycles. | Delay XGKICK by x cycles. | ||
Format: | Format: | ||
Line 779: | Line 779: | ||
0x00000006 | 0x00000000 | 0x00000008 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000006 | 0x00000000 | 0x00000008 | 0x00000000 | 0x00000000 | 0x00000000 | ||
{{ | {{Boxcomm|id=0x07|name=Unknown|data=1x int32|}} | ||
Patch 2 x 32 bit opcodes of VU1 microprogram (lower and upper opcode). Config allow to specify bitmask for both read and write. | Patch 2 x 32 bit opcodes of VU1 microprogram (lower and upper opcode). Config allow to specify bitmask for both read and write. | ||
Format: | Format: | ||
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writeVu1Code(i, 0x000000008000033C & 0x00000000FFFFFFFF) | writeVu1Code(i, 0x000000008000033C & 0x00000000FFFFFFFF) | ||
{{ | {{Boxcomm|id=0x0A|name=Unknown|data=2x uint16|}} | ||
First param can be 0, 1, or 2. Second param in range of 0 and 0xFFFF. Second param is used only if first param == 1. Default values are (1, 0x1000) for PS2DVD, and (1, 0x400) for PS2CD and PS2CDDA. | First param can be 0, 1, or 2. Second param in range of 0 and 0xFFFF. Second param is used only if first param == 1. Default values are (1, 0x1000) for PS2DVD, and (1, 0x400) for PS2CD and PS2CDDA. | ||
Format: | Format: | ||
Line 860: | Line 799: | ||
0x0000000A | 0x00000000 | 0x0001 | 0x0400 | 0x00000000 | 0x00000000 | 0x00000000 | 0x0000000A | 0x00000000 | 0x0001 | 0x0400 | 0x00000000 | 0x00000000 | 0x00000000 | ||
{{ | {{Boxcomm|id=0x0B|name=Unknown|data=1x int32|}} | ||
Command take bool value and default is 1. When set to 0: Skip some IOP related code responsible for check value from IOP SPE (and skip panic if value is 0 or -1).<br> | Command take bool value and default is 1. When set to 0: Skip some IOP related code responsible for check value from IOP SPE (and skip panic if value is 0 or -1).<br> | ||
Also skip write of value 0x80000000 to SPU Signal Notification 1 Register of IOP SPE. | Also skip write of value 0x80000000 to SPU Signal Notification 1 Register of IOP SPE. | ||
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0x0000000B | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x0000000B | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | ||
{{ | {{Boxcomm|id=0x0C|name=Unknown|data=1x int32|}} | ||
Use PS2 accurate add/sub math for selected opcode/offset. Command is valid for every FPU and COP2 opcode that do add/sub (also for opcodes like VMSUBA, MADD, etc). | Use PS2 accurate add/sub math for selected opcode/offset. Command is valid for every FPU and COP2 opcode that do add/sub (also for opcodes like VMSUBA, MADD, etc). | ||
Format: | Format: | ||
Line 873: | Line 812: | ||
0x0000000C | 0x00000000 | 0x001264D4 | 0x00000000 | 0x00000000 | 0x00000000 | 0x0000000C | 0x00000000 | 0x001264D4 | 0x00000000 | 0x00000000 | 0x00000000 | ||
{{ | {{Boxcomm|id=0x0D|name=Unknown|data=2x int32|}} | ||
Use PS2 accurate add/sub math for selected opcode/offsets range. Command is valid for every FPU and COP2 opcode that do add/sub (also for opcodes like VMSUBA, MADD, etc). | Use PS2 accurate add/sub math for selected opcode/offsets range. Command is valid for every FPU and COP2 opcode that do add/sub (also for opcodes like VMSUBA, MADD, etc). | ||
Format: | Format: | ||
Line 879: | Line 818: | ||
0x0000000D | 0x00000000 | 0x0012A3D4 | 0x0012A468 | 0x00000000 | 0x00000000 | 0x0000000D | 0x00000000 | 0x0012A3D4 | 0x0012A468 | 0x00000000 | 0x00000000 | ||
{{ | {{Boxcomm|id=0x0E|name=Unknown|data=2x int32|}} | ||
Use PS2 accurate mul/div math for selected opcode/offsets range. Command is valid for every FPU opcode that do mul/div (also for opcodes like MADD, MSUBA etc). Command does not work for COP2 opcodes. | Use PS2 accurate mul/div math for selected opcode/offsets range. Command is valid for every FPU opcode that do mul/div (also for opcodes like MADD, MSUBA etc). Command does not work for COP2 opcodes. | ||
Format: | Format: | ||
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0x0000000E | 0x00000000 | 0x005719D8 | 0x00571C2C | 0x00000000 | 0x00000000 | 0x0000000E | 0x00000000 | 0x005719D8 | 0x00571C2C | 0x00000000 | 0x00000000 | ||
{{ | {{Boxcomm|id=0x0F|name=Unknown|data=1x int32|}} | ||
Use PS2 accurate add/sub math for selected opcode/offset in VU0 microprogram. Command is valid for every VU0 opcode that do add/sub (also for opcodes like MSUBAQ, MADDAx, etc).<br> | Use PS2 accurate add/sub math for selected opcode/offset in VU0 microprogram. Command is valid for every VU0 opcode that do add/sub (also for opcodes like MSUBAQ, MADDAx, etc).<br> | ||
Valid VU0 memory offset is in range (0x000 to 0xFFF) & 0xFF8, which mean that last nibble needs to be either 0 or 8. <!--Todo: Is it really VU0 offset in plain hex or (offset >> 8)--> | Valid VU0 memory offset is in range (0x000 to 0xFFF) & 0xFF8, which mean that last nibble needs to be either 0 or 8. <!--Todo: Is it really VU0 offset in plain hex or (offset >> 8)--> | ||
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0x0000000F | 0x00000000 | 0x00000208 | 0x00000000 | 0x00000000 | 0x00000000 | 0x0000000F | 0x00000000 | 0x00000208 | 0x00000000 | 0x00000000 | 0x00000000 | ||
{{ | {{Boxcomm|id=0x11|name=Unknown|data=1x int64|}} | ||
Delay memory card related operations by x cycles. | Delay memory card related operations by x cycles. | ||
Format: | Format: | ||
Line 904: | Line 837: | ||
0x00000011 | 0x00000000 | 0x000000000000F960 | 0x00000000 | 0x00000000 | 0x00000011 | 0x00000000 | 0x000000000000F960 | 0x00000000 | 0x00000000 | ||
{{ | {{Boxcomm|id=0x12|name=Unknown|data=None|}} | ||
Use alternative code path during ADD/SUB VU1 recompilation. Config seems to be very specific hack, most likely not usable outside of THPS 4+ engine games.<br> | Use alternative code path during ADD/SUB VU1 recompilation. Config seems to be very specific hack, most likely not usable outside of THPS 4+ engine games.<br> | ||
Note: This setting affects only VU1, and only ADD/SUB. All other opcodes like ADDi,ADDq, MSUB, ADDbc, are not affected. | Note: This setting affects only VU1, and only ADD/SUB. All other opcodes like ADDi,ADDq, MSUB, ADDbc, are not affected. | ||
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0x00000012 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000012 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | ||
{{ | {{Boxcomm|id=0x13|name=Unknown|data=1x int32|}} | ||
Patch SPE 0 (IOP) program in local memory. Command search for absolute branches in LS 0x3A9C0 - 0x3ADC0 and patch first found absolute branch to "bi r127".<br> | Patch SPE 0 (IOP) program in local memory. Command search for absolute branches in LS 0x3A9C0 - 0x3ADC0 and patch first found absolute branch to "bi r127".<br> | ||
This command takes partially unused value. Value 0,1 do nothing, values 2 and above run command. Doesn't matter is 2,4, or 10. Nothing will change in command behavior. | This command takes partially unused value. Value 0,1 do nothing, values 2 and above run command. Doesn't matter is 2,4, or 10. Nothing will change in command behavior. | ||
Line 918: | Line 851: | ||
0x00000013 | 0x00000000 | 0x00000002 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000013 | 0x00000000 | 0x00000002 | 0x00000000 | 0x00000000 | 0x00000000 | ||
{{ | {{Boxcomm|id=0x14|name=Unknown|data=1x int8|}} | ||
Gsgif related command. Unused in latest emu, also seems to be unreachable even if set. | Gsgif related command. Unused in latest emu, also seems to be unreachable even if set. | ||
Format: | Format: | ||
Line 924: | Line 857: | ||
0x00000014 | 0x00000000 | 0x01 | 0x000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000014 | 0x00000000 | 0x01 | 0x000000 | 0x00000000 | 0x00000000 | 0x00000000 | ||
{{ | {{Boxcomm|id=0x15|name=Unknown|data=1x int8|}} | ||
Value is bool, default 0. When set to true, MTC0/MFC0 operation of COP0 Count ($9) register uses ppc timebase register as a base for calculation, when disabled decrementer register is used as a base for calculations. | Value is bool, default 0. When set to true, MTC0/MFC0 operation of COP0 Count ($9) register uses ppc timebase register as a base for calculation, when disabled decrementer register is used as a base for calculations. | ||
Format: | Format: | ||
Line 930: | Line 863: | ||
0x00000015 | 0x00000000 | 0x01 | 0x000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000015 | 0x00000000 | 0x01 | 0x000000 | 0x00000000 | 0x00000000 | 0x00000000 | ||
{{ | {{Boxcomm|id=0x16|name=Unknown|data=None|}} | ||
Perform additional check during GS CSR write and if there is SIGNAL clear bit active and other dependencies are fulfilled, do some additional operations with GS. | Perform additional check during GS CSR write and if there is SIGNAL clear bit active and other dependencies are fulfilled, do some additional operations with GS. | ||
Format: | Format: | ||
32 bit ID | 32 bit ID | 32 bit align | 32 bit align | 32 bit align | 32 bit align | 32 bit align | ||
0x000000016 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x000000016 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | ||