Editing PS2 Emulation/PS2 Config Commands

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Line 792: Line 792:
  if readVu1Code(i) & 0x80000000FFFFFFFF == 0x0000000040000001
  if readVu1Code(i) & 0x80000000FFFFFFFF == 0x0000000040000001
     writeVu1Code(i, 0x000000008000033C & 0x00000000FFFFFFFF)
     writeVu1Code(i, 0x000000008000033C & 0x00000000FFFFFFFF)
{{BoxcommGX|id=0x08|net_id=0x09|data=1x int32|}}
Patch 2 x 32 bit opcodes of EE executable code.
Format:
32 bit ID  | 32 bit align | 64bit ptr to emu memory | 32 bit count | 32 bit align
0x00000008 |  0x00000000  |  0x0000000000341190    |  0x00000002  |  0x00000000
Additional example data at 0x341190 looks like this:
  32 bit EE offset  | 32 bit original opcode | 32 bit original opcode | 32 bit replace opcode | 32 bit replace opcode
    0x00418750    |      0x1062FFFA      |      0x00000000      |      0x00000000      |      0x00000000
due to patch count == 2 in this example, there is next set of data right after first one:
  32 bit EE offset  | 32 bit original opcode | 32 bit original opcode | 32 bit replace opcode | 32 bit replace opcode
    0x00418808    |      0x1062FFFA      |      0x00000000      |      0x00000000      |      0x00000000
{{BoxcommGX|id=0x09|net_id=0x0B|data=1x int32|}}
Patch disc data during read operation. <!--todo: explain lba/offset.. offset.-->
Format:
32 bit ID  | 32 bit align | 64bit ptr to emu memory | 32 bit count | 32 bit align
0x00000009 |  0x00000000  |  0x0000000000341190    |  0x00000001  |  0x00000000
Additional example data at 0x341190 looks like this:
  32 bit lba | 32 bit offset in lba | 64 bit ptr to replace data | 64 bit ptr to original data | 32 bit data size in bytes | 32 bit align
  0x00000471 |      0x00000280      |    0x00000000003411B0    |    0x00000000003411B4      |        0x00000004        |  0x00000000


{{BoxcommGX|id=0x0A|net_id=0x0C|data=2x uint16|}}
{{BoxcommGX|id=0x0A|net_id=0x0C|data=2x uint16|}}
Line 925: Line 901:
  Format:
  Format:
  32 bit ID  | 32 bit align | 8 bit data | 24 bit align | 32 bit align | 32 bit align | 32 bit align
  32 bit ID  | 32 bit align | 8 bit data | 24 bit align | 32 bit align | 32 bit align | 32 bit align
  0x0000001A |  0x00000000  |    0x01    |  0x000000  |  0x00000000  |  0x00000000  |  0x00000000
  0x00000015 |  0x00000000  |    0x01    |  0x000000  |  0x00000000  |  0x00000000  |  0x00000000
 
{{BoxcommGX|id=0x1B|net_id=0x1E|data=1x int8|}}
Unknown. Probably mtap related. Command is a 2 bit bitfield. Default value 0
Format:
32 bit ID  | 32 bit align | 8 bit data | 24 bit align | 32 bit align | 32 bit align | 32 bit align
0x0000001B |  0x00000000  |    0x01    |  0x000000  |  0x00000000  |  0x00000000  |  0x00000000
 
{{BoxcommGX|id=0x1C|net_id=0x1F|data=1x int32|}}
Make VIF0 commands MSCAL/MSCALF/MSCNT/MPG/FLUSHE non instant.<br>By default every VIF0 command take 1 cycle, so it's instant.
This config give vif0 some timing sense. Value is cycle count before first event check related to VIF0.<br>
When delta from config passed and vif0 is still running, add 500 cycles and go on until next event test.<br>
This can also be used to ensure that next vif0 command after MSCAL/MSCALF/MSCNT/MPG/FLUSHE won't run until delta from config passed.
Format:
32 bit ID  | 32 bit align | 32 bit data | 32 bit align | 32 bit align | 32 bit align
0x0000001C |  0x00000000  | 0x000003F8  |  0x00000000  |  0x00000000  |  0x00000000
 
{{BoxcommGX|id=0x1D|net_id=0x20|data=1x int64|}}
Vblank timing related, still partially unknown.
Format:
32 bit ID  | 32 bit align |    64 bit data    | 32 bit align | 32 bit align
0x0000001D |  0x00000000  | 0x00000000000000C8 |  0x00000000  |  0x00000000
 
{{BoxcommGX|id=0x1E|net_id=0x21|data=1x int32|}}
Option one default value = 1, when set to 0: r5900 CACHE opcode IXLTG store 0 in COP0 TagLo register. More than that recompiler skip function responsible for analyze and emitting costly iCache checks.<br>
This drastically reduce emitted code size, and practically disable iCache emulation. Additionally CACHE IXIN/IHIN opcodes use different very long code path (this can be skipped with cmd 0x03).<br>
Option two default value = 0, when set to 1: Emit some kind of check for current r5900 PC with possible trap opcode at the end. 1 is valid only when option one is 0.
*0 = sets an option one to 0 and option two to 0
*1 = sets an option one to 0 and option two to 1
*2 = sets an option one to 1 and option two to 0 (default)
Format:
32 bit ID  | 32 bit align | 32 bit data | 32 bit align | 32 bit align | 32 bit align
0x0000001E |  0x00000000  | 0x00000002  |  0x00000000  |  0x00000000  |  0x00000000
 
{{BoxcommGX|id=0x1F|net_id=0x23|data=None|}}
Patch spe 4 program with new custom VIF1 STCYCL alike command 08h handler.
This command is useful only with additional 0x00 hooks. Said hooks inject 08h VIF1 command into game code when other conditions are met.
Format:
32 bit ID  | 32 bit align | 32 bit align | 32 bit align | 32 bit align | 32 bit align
0x0000001F |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000
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