Editing PS2 Emulation/PS2 Config Commands

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=PS2 Netemu Commands=
==PS2 Netemu Commands==


<!-- We need to find a better way to organize the commands info below, right now all the info is "constricted" inside the same table but is better to take them out of the table to have more freedon when adding comments, etc... Are a lot so by now i prefer to dont make page sections for every command. Im going to try something that visually looks like page sections but are not (so are not going to be displayed in the TOC at top of the page). With this change we are moving forward because the command info is not going to be inside the same table anymore, im going to split them but the visual look and other details are not going to be definitive because later can be converted into page sections if someone insists in it -->
<!-- We need to find a better way to organize the commands info below, right now all the info is "constricted" inside the same table but is better to take them out of the table to have more freedon when adding comments, etc... Are a lot so by now i prefer to dont make page sections for every command. Im going to try something that visually looks like page sections but are not (so are not going to be displayed in the TOC at top of the page). With this change we are moving forward because the command info is not going to be inside the same table anymore, im going to split them but the visual look and other details are not going to be definitive because later can be converted into page sections if someone insists in it -->
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{{Boxcomm|id=0x50|name=Enable pressure sensitive controls|data=N/A}}
{{Boxcomm|id=0x50|name=Enable pressure sensitive controls|data=N/A}}


=PS2 Gxemu Commands=
==PS2 Gxemu Commands==
PS2 GX Emu commands are Big Endian unless noted. Every command size is 0x18, and unused data need to be filled with zeros. Commands which point to emulator memory have additional data, but command itself is still 0x18 in size. Data fields are just example values and can be changed to different value when needed.  
PS2 GX Emu commands are Big Endian unless noted. Every command size is 0x18, and unused data need to be filled with zeros. Commands which point to emulator memory have additional data, but command itself is still 0x18 in size. Data fields are just example values and can be changed to different value when needed.  
{{BoxcommGX|id=0x01|net_id=0x02|data=1x int32|}}
{{Boxcomm|id=0x01|name=Unknown|data=1x int32|}}
Used in function that handle D6 CHCR writes (SIF1), seems to be some kind of timing command for EE --> IOP DMA.
Used in function that handle D6 CHCR writes (SIF1), seems to be some kind of timing command for EE --> IOP DMA.
  Format:
  Format:
  32 bit ID  | 32 bit align | 32 bit data | 32 bit align | 32 bit align | 32 bit align
  32 bit ID  | 32 bit align | 32bit data | 32 bit align | 32 bit align | 32 bit align
  0x00000001 |  0x00000000  | 0x00000BB8 |  0x00000000  |  0x00000000  |  0x00000000
  0x00000001 |  0x00000000  | 0x00000BB8 |  0x00000000  |  0x00000000  |  0x00000000


{{BoxcommGX|id=0x02|net_id=0x03|data=None|}}
{{Boxcomm|id=0x02|name=Unknown|data=None|}}
Skip r5900 CACHE IXIN/IHIN (Index/Hit invalidate) opcodes.
Skip r5900 CACHE IXIN/IHIN (Index/Hit invalidate) opcodes.
  Format:
  Format:
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  0x00000002 |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000
  0x00000002 |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000


{{BoxcommGX|id=0x03|net_id=0x04|data=1x int32|}}
{{Boxcomm|id=0x03|name=Unknown|data=1x int32|}}
Patch SPE 4 program (eedma) by searching for ila r4, xxxxx, starting at 0x178A0 and replacing them with (0x42000004 | ((value << 7) & 0x1FFFF80) 0x42000004 is ila r4 opcode. Due to opcode encoding example result of that patch with value 0x08 will be 0x42000404 (ila r4, 0x08). There is little bit more than that, but main purpose is just to patch SPE program behavior.
Patch SPE 4 program (eedma) by searching for ila r4, xxxxx, starting at 0x178A0 and replacing them with (0x42000004 | ((value << 7) & 0x1FFFF80) 0x42000004 is ila r4 opcode. Due to opcode encoding example result of that patch with value 0x08 will be 0x42000404 (ila r4, 0x08). There is little bit more than that, but main purpose is just to patch SPE program behavior.
  Format:
  Format:
  32 bit ID  | 32 bit align | 32 bit data | 32 bit align | 32 bit align | 32 bit align
  32 bit ID  | 32 bit align | 32bit data | 32 bit align | 32 bit align | 32 bit align
  0x00000003 |  0x00000000  | 0x00000008 |  0x00000000  |  0x00000000  |  0x00000000
  0x00000003 |  0x00000000  | 0x00000008 |  0x00000000  |  0x00000000  |  0x00000000


{{BoxcommGX|id=0x04|net_id=Not available|data=None|}}
{{Boxcomm|id=0x04|name=Unknown|data=None|}}
Patch spe 4 program to use alternative VIF1 Direct/DirectHL command handler.
Patch spe 4 program to use alternative VIF1 Direct/DirectHL command handler.
  Format:
  Format:
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  0x00000004 |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000
  0x00000004 |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000


{{BoxcommGX|id=0x05|net_id=0x06|data=None|}}
{{Boxcomm|id=0x05|name=Unknown|data=None|}}
Patch spe 4 program to use alternative VIF1 Offset command handler.
Patch spe 4 program to use alternative VIF1 Offset command handler.
  Format:
  Format:
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  0x00000005 |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000
  0x00000005 |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000


{{BoxcommGX|id=0x06|net_id=0x07|data=1x int32|}}
{{Boxcomm|id=0x06|name=Unknown|data=1x int32|}}
Delay XGKICK by x cycles.
Delay XGKICK by x cycles.
  Format:
  Format:
  32 bit ID  | 32 bit align | 32 bit data | 32 bit align | 32 bit align | 32 bit align
  32 bit ID  | 32 bit align | 32bit data | 32 bit align | 32 bit align | 32 bit align
  0x00000006 |  0x00000000  | 0x00000008 |  0x00000000  |  0x00000000  |  0x00000000
  0x00000006 |  0x00000000  | 0x00000008 |  0x00000000  |  0x00000000  |  0x00000000
 
{{BoxcommGX|id=0x07|net_id=0x08|data=1x int32|}}
Patch 2 x 32 bit opcodes of VU1 microprogram (lower and upper opcode). Config allow to specify bitmask for both read and write.
Format:
32 bit ID  | 32 bit align | 64bit ptr to emu memory | 32 bit align | 32 bit align
0x00000007 |  0x00000000  |  0x0000000000341190    |  0x00000000  |  0x00000000
 
Additional example data at 0x341190 looks like this:
  64 bit read mask  | 64 bit read value  | 64 bit write mask  | 64 bit write value
0x80000000FFFFFFFF | 0x0000000040000001 | 0x00000000FFFFFFFF | 0x000000008000033C
 
Which translates to C:
if readVu1Code(i) & 0x80000000FFFFFFFF == 0x0000000040000001
    writeVu1Code(i, 0x000000008000033C & 0x00000000FFFFFFFF)
 
{{BoxcommGX|id=0x08|net_id=0x09|data=1x int32|}}
Patch 2 x 32 bit opcodes of EE executable code.
Format:
32 bit ID  | 32 bit align | 64bit ptr to emu memory | 32 bit count | 32 bit align
0x00000008 |  0x00000000  |  0x0000000000341190    |  0x00000002  |  0x00000000
 
Additional example data at 0x341190 looks like this:
  32 bit EE offset  | 32 bit original opcode | 32 bit original opcode | 32 bit replace opcode | 32 bit replace opcode
    0x00418750    |      0x1062FFFA      |      0x00000000      |      0x00000000      |      0x00000000
due to patch count == 2 in this example, there is next set of data right after first one:
  32 bit EE offset  | 32 bit original opcode | 32 bit original opcode | 32 bit replace opcode | 32 bit replace opcode
    0x00418808    |      0x1062FFFA      |      0x00000000      |      0x00000000      |      0x00000000
 
{{BoxcommGX|id=0x09|net_id=0x0B|data=1x int32|}}
Patch disc data during read operation. <!--todo: explain lba/offset.. offset.-->
Format:
32 bit ID  | 32 bit align | 64bit ptr to emu memory | 32 bit count | 32 bit align
0x00000009 |  0x00000000  |  0x0000000000341190    |  0x00000001  |  0x00000000
 
Additional example data at 0x341190 looks like this:
  32 bit lba | 32 bit offset in lba | 64 bit ptr to replace data | 64 bit ptr to original data | 32 bit data size in bytes | 32 bit align
  0x00000471 |      0x00000280      |    0x00000000003411B0    |    0x00000000003411B4      |        0x00000004        |  0x00000000
 
{{BoxcommGX|id=0x0A|net_id=0x0C|data=2x uint16|}}
First param can be 0, 1, or 2. Second param in range of 0 and 0xFFFF. Second param is used only if first param == 1. Default values are (1, 0x1000) for PS2DVD, and (1, 0x400) for PS2CD and PS2CDDA.
Format:
32 bit ID  | 32 bit align | 16 bit data | 16 bit data | 32 bit align | 32 bit align | 32 bit align
0x0000000A |  0x00000000  |    0x0001  |    0x0400  |  0x00000000  |  0x00000000  |  0x00000000
 
{{BoxcommGX|id=0x0B|net_id=0x0D|data=1x int32|}}
Command take bool value and default is 1. When set to 0: Skip some IOP related code responsible for check value from IOP SPE (and skip panic if value is 0 or -1).<br>
Also skip write of value 0x80000000 to SPU Signal Notification 1 Register of IOP SPE.
Format:
32 bit ID  | 32 bit align | 32 bit data | 32 bit align | 32 bit align | 32 bit align
0x0000000B |  0x00000000  | 0x00000000  |  0x00000000  |  0x00000000  |  0x00000000
 
{{BoxcommGX|id=0x0C|net_id=0x0E|data=1x int32|}}
Use PS2 accurate add/sub math for selected opcode/offset. Command is valid for every FPU and COP2 opcode that do add/sub (also for opcodes like VMSUBA, MADD, etc).
Format:
32 bit ID  | 32 bit align | 32 bit EE memory offset | 32 bit align | 32 bit align | 32 bit align
0x0000000C |  0x00000000  |      0x001264D4        |  0x00000000  |  0x00000000  |  0x00000000
 
{{BoxcommGX|id=0x0D|net_id=0x0F|data=2x int32|}}
Use PS2 accurate add/sub math for selected opcode/offsets range. Command is valid for every FPU and COP2 opcode that do add/sub (also for opcodes like VMSUBA, MADD, etc).
Format:
32 bit ID  | 32 bit align | 32 bit EE start memory offset | 32bit EE end memory offset | 32 bit align | 32 bit align
0x0000000D |  0x00000000  |          0x0012A3D4          |        0x0012A468        |  0x00000000  |  0x00000000
 
{{BoxcommGX|id=0x0E|net_id=0x10|data=2x int32|}}
Use PS2 accurate mul/div math for selected opcode/offsets range. Command is valid for every FPU opcode that do mul/div (also for opcodes like MADD, MSUBA etc). Command does not work for COP2 opcodes.
Format:
32 bit ID  | 32 bit align | 32 bit EE start memory offset | 32bit EE end memory offset | 32 bit align | 32 bit align
0x0000000E |  0x00000000  |          0x005719D8          |        0x00571C2C        |  0x00000000  |  0x00000000
 
{{BoxcommGX|id=0x0F|net_id=0x11|data=1x int32|}}
Use PS2 accurate add/sub math for selected opcode/offset in VU0 microprogram. Command is valid for every VU0 opcode that do add/sub (also for opcodes like MSUBAQ, MADDAx, etc).<br>
Valid VU0 memory offset is in range (0x000 to 0xFFF) & 0xFF8, which mean that last nibble needs to be either 0 or 8. <!--Todo: Is it really VU0 offset in plain hex or (offset >> 8)-->
Format:
32 bit ID  | 32 bit align | 32 bit VU0 memory offset | 32 bit align | 32 bit align | 32 bit align
0x0000000F |  0x00000000  |        0x00000208        |  0x00000000  |  0x00000000  |  0x00000000
 
{{BoxcommGX|id=0x10|net_id=0x12|data=1x int64, 1x int32|}}
Multi-purpose VU0/COP2 command. Data size vary depending on sub commands, but at least 2 x 32 bit is required to make command valid.
Format:
32 bit ID  | 32 bit align | 64 bit ptr to emu memory with data | Data size / 4 | 32 bit align
0x00000010 |  0x00000000  |        0x0000000000323288        |  0x0000000D  |  0x00000000
 
{{BoxcommGX|id=0x11|net_id=0x13|data=1x int64|}}
Delay memory card related operations by x cycles.
Format:
32 bit ID  | 32 bit align |    64 bit data    | 32 bit align | 32 bit align
0x00000011 |  0x00000000  | 0x000000000000F960 |  0x00000000  |  0x00000000
 
{{BoxcommGX|id=0x12|net_id=0x14|data=None|}}
Use alternative code path during ADD/SUB VU1 recompilation. Config seems to be very specific hack, most likely not usable outside of THPS 4+ engine games.<br>
Note: This setting affects only VU1, and only ADD/SUB. All other opcodes like ADDi,ADDq, MSUB, ADDbc, are not affected.
Format:
32 bit ID  | 32 bit align | 32 bit align | 32 bit align | 32 bit align | 32 bit align
0x00000012 |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000
 
{{BoxcommGX|id=0x13|net_id=0x15|data=1x int32|}}
Patch SPE 0 (IOP) program in local memory. Command search for absolute branches in LS 0x3A9C0 - 0x3ADC0 and patch first found absolute branch to "bi r127".<br>
This command takes partially unused value. Value 0,1 do nothing, values 2 and above run command. Doesn't matter is 2,4, or 10. Nothing will change in command behavior.
Format:
32 bit ID  | 32 bit align | 32 bit data | 32 bit align | 32 bit align | 32 bit align
0x00000013 |  0x00000000  | 0x00000002  |  0x00000000  |  0x00000000  |  0x00000000
 
{{BoxcommGX|id=0x14|net_id=Not available|data=1x int8|}}
Gsgif related command. Unused in latest emu, also seems to be unreachable even if set.
Format:
32 bit ID  | 32 bit align | 8 bit data | 24 bit align | 32 bit align | 32 bit align | 32 bit align
0x00000014 |  0x00000000  |    0x01    |  0x000000  |  0x00000000  |  0x00000000  |  0x00000000
 
{{BoxcommGX|id=0x15|net_id=0x17|data=1x int8|}}
Value is bool, default 0. When set to true, MTC0/MFC0 operation of COP0 Count ($9) register uses ppc timebase register as a base for calculation, when disabled decrementer register is used as a base for calculations.
Format:
32 bit ID  | 32 bit align | 8 bit data | 24 bit align | 32 bit align | 32 bit align | 32 bit align
0x00000015 |  0x00000000  |    0x01    |  0x000000  |  0x00000000  |  0x00000000  |  0x00000000
 
{{BoxcommGX|id=0x16|net_id=Not available|data=None|}}
Perform additional check during GS CSR write and if there is SIGNAL clear bit active and other dependencies are fulfilled, do some additional operations with GS.
Format:
32 bit ID  | 32 bit align | 32 bit align | 32 bit align | 32 bit align | 32 bit align
0x000000016 |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000
 
{{BoxcommGX|id=0x17|net_id=0x1A|data=None|}}
IPU BCLR command hack <!--todo-->
Format:
32 bit ID  | 32 bit align | 32 bit align | 32 bit align | 32 bit align | 32 bit align
0x00000017 |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000
 
{{BoxcommGX|id=0x18|net_id=0x1B|data=None|}}
IPU IDEC command hack <!--todo-->
Format:
32 bit ID  | 32 bit align | 32 bit align | 32 bit align | 32 bit align | 32 bit align
0x00000018 |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000
 
{{BoxcommGX|id=0x19|net_id=Not available|data=None|}}
Disable DEV9. Disables net/ps2hdd capabilities including Network Adapter detection.
Format:
32 bit ID  | 32 bit align | 32 bit align | 32 bit align | 32 bit align | 32 bit align
0x00000019 |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000
 
{{BoxcommGX|id=0x1A|net_id=0x1D|data=1x int8|}}
Sets multitap to specific controller ports and adjusts the order of ports to which controllers are synced. Default 3
*0 = no multitap set (only when needed). Controller sync order: 1/1-A, 2/2-A, 1-B, 2-B...
*1 = sets multitap in controller port 1 at all times. Controller sync order: 1/1-A, 1-B, 1-C, 1-D...
*2 = sets multitap in controller port 2 at all times. Controller sync order: 1/1-A, 2/2-A, 2-B, 2-C...
*3 = sets multitaps in both controller ports at all times. Controller sync order: same as 0
Format:
32 bit ID  | 32 bit align | 8 bit data | 24 bit align | 32 bit align | 32 bit align | 32 bit align
0x0000001A |  0x00000000  |    0x01    |  0x000000  |  0x00000000  |  0x00000000  |  0x00000000
 
{{BoxcommGX|id=0x1B|net_id=0x1E|data=1x int8|}}
Unknown. Probably mtap related. Command is a 2 bit bitfield. Default value 0
Format:
32 bit ID  | 32 bit align | 8 bit data | 24 bit align | 32 bit align | 32 bit align | 32 bit align
0x0000001B |  0x00000000  |    0x01    |  0x000000  |  0x00000000  |  0x00000000  |  0x00000000
 
{{BoxcommGX|id=0x1C|net_id=0x1F|data=1x int32|}}
Make VIF0 commands MSCAL/MSCALF/MSCNT/MPG/FLUSHE non instant.<br>By default every VIF0 command take 1 cycle, so it's instant.
This config give vif0 some timing sense. Value is cycle count before first event check related to VIF0.<br>
When delta from config passed and vif0 is still running, add 500 cycles and go on until next event test.<br>
This can also be used to ensure that next vif0 command after MSCAL/MSCALF/MSCNT/MPG/FLUSHE won't run until delta from config passed.
Format:
32 bit ID  | 32 bit align | 32 bit data | 32 bit align | 32 bit align | 32 bit align
0x0000001C |  0x00000000  | 0x000003F8  |  0x00000000  |  0x00000000  |  0x00000000
 
{{BoxcommGX|id=0x1D|net_id=0x20|data=1x int64|}}
Vblank timing related, still partially unknown.
Format:
32 bit ID  | 32 bit align |    64 bit data    | 32 bit align | 32 bit align
0x0000001D |  0x00000000  | 0x00000000000000C8 |  0x00000000  |  0x00000000
 
{{BoxcommGX|id=0x1E|net_id=0x21|data=1x int32|}}
Option one default value = 1, when set to 0: r5900 CACHE opcode IXLTG store 0 in COP0 TagLo register. More than that recompiler skip function responsible for analyze and emitting costly iCache checks.<br>
This drastically reduce emitted code size, and practically disable iCache emulation. Additionally CACHE IXIN/IHIN opcodes use different very long code path (this can be skipped with cmd 0x03).<br>
Option two default value = 0, when set to 1: Emit some kind of check for current r5900 PC with possible trap opcode at the end. 1 is valid only when option one is 0.
*0 = sets an option one to 0 and option two to 0
*1 = sets an option one to 0 and option two to 1
*2 = sets an option one to 1 and option two to 0 (default)
Format:
32 bit ID  | 32 bit align | 32 bit data | 32 bit align | 32 bit align | 32 bit align
0x0000001E |  0x00000000  | 0x00000002  |  0x00000000  |  0x00000000  |  0x00000000
 
{{BoxcommGX|id=0x1F|net_id=0x23|data=None|}}
Patch spe 4 program with new custom VIF1 STCYCL alike command 08h handler.
This command is useful only with additional 0x00 hooks. Said hooks inject 08h VIF1 command into game code when other conditions are met.
Format:
32 bit ID  | 32 bit align | 32 bit align | 32 bit align | 32 bit align | 32 bit align
0x0000001F |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000  |  0x00000000
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