Editing PCIe
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Bus, resembling [https://en.wikipedia.org/wiki/PCI_Express Conventional PCIe] x4 1.0, partly connected to [[South Bridge]], with 200 exposed pads.<br> | Bus, resembling [https://en.wikipedia.org/wiki/PCI_Express Conventional PCIe] x4 1.0, partly connected to [[South Bridge]], with 200 exposed pads.<br> | ||
Can be activated by setting the [[Repository_Nodes|Repository Node]] ''sys.lv1.iosys.pciex'' to ''1'' (in [[sysctl.txt]]). The PCIe MMIO address space can be extended to 1GB by setting ''sys.lv1.large_pciex'' to ''1''.<br> | Can be activated by setting the [[Repository_Nodes|Repository Node]] ''sys.lv1.iosys.pciex'' to ''1'' (in [[sysctl.txt]]). The PCIe MMIO address space can be extended to 1GB by setting ''sys.lv1.large_pciex'' to ''1''.<br> | ||
The [[Hypervisor_Reverse_Engineering|Hypervisor]] does not allow all PCIe device to be used with this connector, the check can e.g. be found in ''sub_2355B4'' ([[lv1.self]], [[4.81 DECR]]). | |||
=== 200-pin layout === | === 200-pin layout === |