Editing PCIe
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== PCIe == | == PCIe == | ||
Bus, resembling | Bus, resembling Conventional PCIe x4 1.0, partly connected to [[South Bridge]], with 200 exposed pads.<br/> | ||
Can be activated by setting the | Can be activated by setting the repository node ''sys.lv1.iosys.pciex'' to ''1''. The PCIe MMIO address space can be extended to 1GB by setting ''sys.lv1.large_pciex'' to ''1''. | ||
=== 200-pin layout === | === 200-pin layout === | ||
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{| class="wikitable sortable" | {| class="wikitable sortable" | ||
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! Pin !! Usage !! | ! Pin !! Usage !! Standardized Pinout !! Remark | ||
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| 1 || GND || || | | 1 || GND || || |