Editing PCI
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<div style="float:right">[[File:PCI pads - as seen on COK-002.jpg|200px|thumb|left|PCI pads - as seen on COK-002<br>note: Two circular pads in the bottom right corner are for southbridge serial | <div style="float:right">[[File:PCI pads - as seen on COK-002.jpg|200px|thumb|left|File:PCI pads - as seen on COK-002<br />note: Two circular pads in the bottom right corner are for southbridge serial]]</div> | ||
== PCI == | == PCI == | ||
Bus, resembling Conventional PCI 2.3, directly connected to [[South Bridge]], with 80 exposed pads | Bus, resembling Conventional PCI 2.3, directly connected to [[South Bridge]], with 80 exposed pads | ||
Major differences from PCI standard: | Major differences from PCI standard: | ||
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* no support for optional JTAG signals, nor for the 64-bit PCI extension defined in the PCI Local Bus Specification | * no support for optional JTAG signals, nor for the 64-bit PCI extension defined in the PCI Local Bus Specification | ||
=== | === 80 pin miniPCI pad layout === | ||
CN3208 80P on [[CECHAxx]]/[[CECHBxx]] [[COK-00x#COK-001|COK-001]] | CN3208 80P on [[CECHAxx]]/[[CECHBxx]] [[COK-00x#COK-001|COK-001]] and [[CECHCxx]]/[[CECHExx]] [[COK-00x#COK-002|COK-002]] | ||
CN3208 70P on [[CECHGxx]] [[SEM-00x | CN3208 70P on [[CECHGxx]] [[SEM-00x|SEM-001]] | ||
{| class="wikitable sortable" | {| class="wikitable sortable" | ||
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|} | |} | ||
=== [[South Bridge]] serial === | |||
{| class="wikitable sortable" | {| class="wikitable sortable" | ||
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|- | |- | ||
|} | |} | ||