View source for Hardware Flashers:NAND pinout

= NAND Consoles =
These are the earliest revisions of the PS3 motherboards: [[CECHAxx|CECHA]]/[[COK-00x|COK-001]], [[CECHBxx|CECHB]]/[[COK-00x|COK-001]], [[CECHCxx|CECHC]]/[[COK-00x|COK-002]], [[CECHExx|CECHE]]/[[COK-00x|COK-002W]], [[CECHGxx|CECHG]]/[[SEM-00x|SEM-001]] and contain 2x NAND chips for a total of 256MB. These chips are interleaved which is controlled by a proprietary controller chip codenamed "[[Starship2]]" or SS2. This chip handles the interleaving and presents the NAND Chips to the [[South Bridge]] as a single large coherent flash over a proprietary EBUS.

== NAND Wiring ==
Flashers for NAND based consoles ([[CECHAxx|CECHA]]/[[COK-00x#COK-001|COK-001]], [[CECHBxx|CECHB]]/[[COK-00x#COK-001|COK-001]], [[CECHCxx|CECHC]]/[[COK-00x#COK-002|COK-002]], [[CECHDxx|CECHD]]/unreleased, [[CECHExx|CECHE]]/[[COK-00x#COK-002W|COK-002W]], [[CECHFxx|CECHF]]/unreleased, [[CECHGxx|CECHG]]/[[SEM-00x|SEM-001]]) are generaly wired directly to the pins of the NAND ('''you cannot use the testpoints!''' between [[Southbridge]] and [[Starship2]]), plus ground and Vcc. Alternatively, boardtraces (between [[Starship2]] and [[NAND]]) can be used.

=== Which NAND is low/high? ===
* [[COK-00x#COK-001|COK-001]] :
** IC3802 LOW (main componentside with SATA connector, [[CELL BE]], [[RSX]] etc. next to [[Starship2]])
** IC3803 HIGH (backside next to 60-pin BD ATA connector) 

* [[COK-00x#COK-002|COK-002]] + [[COK-00x#COK-002W|COK-002W]] :
** [[:File:CECHC NAND-IC3802.JPG|IC3802 LOW]] (main componentside with SATA connector, [[CELL BE]], [[RSX]] etc. between SATA connector and [[South Bridge]])
** [[:File:CECHC-NAND-IC3803.JPG|IC3803 HIGH]] (main componentside with SATA connector, [[CELL BE]], [[RSX]] etc. between SATA connector and [[Connectors#CN2401_12P|AV Multi connector]])

* [[SEM-00x|SEM-001]] :
** IC3802 LOW (backside)
** IC3803 HIGH (main componentside with SATA connector, [[CELL BE]], [[RSX]] etc.)

=== EBUS Interface Testpoints on NAND consoles ===
Simular as on the NOR based consoles, testpoints can be found on the back of the PCB. It seems these are from the EBUS between the [[South Bridge]] and the [[Starship2]]. Attempts have been made to document/trace these. Addresslines 0-17 and Datalines 0-15 as well as some controllines are documented but so far these ''could not be used to read/flash the console''.

=== TriState on NAND consoles ===
using [[Starship2]] to southbridge /SB_EBUS_ACK @ SB_MAIN(P30)  (numbered 52 in [[:File:SS2_NOR.JPG]])
* CECHA (COK-001): IC3801:CXD4302GB-T6 pin:C1/ ebus jl:9308 (page 20 of [https://web.archive.org/web/*/http://ps3devwiki.com/files/documents/-PS3%20Service%20Manuals/ servicemanual])
* CECHC + CECHE (COK-002): IC3801:CXD4302GB-T6 pin:C1/ ebus jl:9308 (page 20 of [https://web.archive.org/web/*/http://ps3devwiki.com/files/documents/-PS3%20Service%20Manuals/ servicemanual])
* CECHG (SEM001): IC3801:CXD9909GB pin:C1/ ebus jl:9308 (page 21 of [https://web.archive.org/web/*/http://ps3devwiki.com/files/documents/-PS3%20Service%20Manuals/ servicemanual])

=== NAND Pinout table ===
{{NAND-Flashertable}}

== Structure ==
There are 2 NAND used, interleaved at 512byte/sector level, giving it a 1024 byte "interleaved sector". Pages are 2kb on each NAND.


{{Hardware Flashers}}<noinclude>[[Category:Main]]</noinclude>