Editing HV Syscall Reference
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Latest revision | Your text | ||
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|- | |- | ||
|R3 | |R3 | ||
|status | |status | ||
|- | |- | ||
|R4 | |R4 | ||
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|} | |} | ||
---- | ---- | ||
=== lv1_write_remote_file === | === lv1_write_remote_file === | ||
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===== Kernel Call ===== | ===== Kernel Call ===== | ||
result = lv1_allocate_device_dma_region( /*IN*/ bus_id, dev_id, io_size, io_pagesize, flag, | result = lv1_allocate_device_dma_region( /*IN*/ bus_id, dev_id, io_size, io_pagesize, flag, &dma_region ); | ||
===== Parameters ===== | ===== Parameters ===== | ||
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Notes: When the device is little endian, the mode must be set to 8 bit for 8 bit DMA to work as expected, otherwise the bytes will be read/written in the wrong order. OTOH, this mode requires that 16 and 32-bit values are byte-swapped by the CPU since they will appear as little endian in memory. | Notes: When the device is little endian, the mode must be set to 8 bit for 8 bit DMA to work as expected, otherwise the bytes will be read/written in the wrong order. OTOH, this mode requires that 16 and 32-bit values are byte-swapped by the CPU since they will appear as little endian in memory. | ||
---- | ---- | ||
=== lv1_free_device_dma_region === | === lv1_free_device_dma_region === | ||
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|R4 | |R4 | ||
|IRQ Bitmap of all pending IRQ’s. This is a bitset. | |IRQ Bitmap of all pending IRQ’s. This is a bitset. | ||
0 | A bit = 0 means IRQ not pending, 1 = IRQ pending. | ||
Bit GPU_INTR_STATUS_VSYNC_0 = 0. IRQ for vsync on head A. Unused by Kernel | |||
Bit GPU_INTR_STATUS_VSYNC_1 = 1. IRQ for vsync on head B. Used by Kernel | |||
Bit GPU_INTR_STATUS_FLIP_0 = 2. IRQ for flip on head A. Unused by Kernel | |||
Bit GPU_INTR_STATUS_FLIP_1 = 3. IRQ for flip on head B. Unused by Kernel | |||
Bit GPU_INTR_STATUS_QUEUE_0 = 4. IRQ for queue on head A. Unused by Kernel | |||
Bit GPU_INTR_STATUS_QUEUE_1 = 5. IRQ for queue on head B. Unused by Kernel | |||
|- | |- | ||
|} | |} | ||
---- | ---- | ||
=== lv1_gpu_attribute === | === lv1_gpu_attribute === | ||