Editing HV Syscall Reference

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=== lv1_detect_pending_interrupts ===
=== lv1_detect_pending_interrupts ===


Not used in current kernel. Used in ps2_gxemu.
Not used in current kernel.


===== Abstract Call =====
===== Abstract Call =====
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|-
|-
|R3
|R3
|p1 - unknown (only 0 value is supported)
|p1 - unknown
|-
|-
! colspan="2" | Outputs
! colspan="2" | Outputs
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|-
|-
|R3
|R3
|Status
|Status?
|-
|-
|R4
|R4
|v1 - irq_bitmap[0]
|v1 - Unknown
|-
|-
|R5
|R5
|v2 - irq_bitmap[1]
|v2 - Unknown
|-
|-
|R6
|R6
|v3 - irq_bitmap[2]
|v3 - Unknown
|-
|-
|R7
|R7
|v4 - irq_bitmap[3]
|v4 - Unknown
|-
|-
|}
|}


Notes:<br>
Notes:
Return 256 bit irq bitmap for previously connected irq plugs (using lv1_connect_irq_plug).<br>
 
Info taken from kboot-10\dl\linux-2.6.16\include\asm-powerpc\lv1calltab.h (kboot-20061208)
Info taken from kboot-10\dl\linux-2.6.16\include\asm-powerpc\lv1calltab.h (kboot-20061208)
----
----
=== lv1_end_of_interrupt ===
=== lv1_end_of_interrupt ===


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=== lv1_set_dabr ===
=== lv1_set_dabr ===


Sets dabr (Data Address Breakpoint Register) and dabrx (Data Address Breakpoint Register Extension)
Sets dabr (data address breakpoint register) - an exception should be thrown upon access to data at this address (range?)


===== Kernel Call =====
===== Kernel Call =====


  result = lv1_set_dabr( /*IN*/ dabr, dabrx);
  result = lv1_set_dabr( /*IN*/ dabr, DABR_KERNEL | DABR_USER);


===== Parameters =====
===== Parameters =====
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|-
|-
|R3
|R3
|dabr - see notes
|dabr - data address
|-
|-
|R4
|R4
|dabrx - see notes
|(DABR_KERNEL | DABR_USER) - see notes
|-
|-
! colspan="2" | Outputs
! colspan="2" | Outputs
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Notes:
Notes:
*DABR:
Bit(s) Name Description
0:60  DAB  Data Address Breakpoint
61    BT  Breakpoint Translation
62    DW  Data Write
63    DR  Data Read


*DABRX
DABR_KERNEL and DABR_USER are defined in “setup.c” as follows
Bit(s) Name  Description
0:59        Reserved
60    BTI  Breakpoint Translation Ignore
61:63  PRIVM Privilege Mask
61    HYP  Hypervisor state - unsupported in LV1
62    PNH  Privileged but Non-Hypervisor state
63    PRO  Problem state
When PRIVM in dabrx is 0 or when any unsupported or reserved bit in dabrx is active, both dabr and dabrx writes are not performed and 0x2FFFFFFEF is returned. <br><br>
DABRX is defined in “setup.c” as follows
  enum {DABR_USER = 1, DABR_KERNEL = 2,};
  enum {DABR_USER = 1, DABR_KERNEL = 2,};
----
----
=== lv1_set_vmx_graphics_mode ===
=== lv1_set_vmx_graphics_mode ===


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The Cell Broadband Engine Programming Handbook has this to say on the subject: The first implementation of the Cell Broadband Engine Architecture (CBEA) (the CBE processor) supports instructions with a graphics rounding mode. This mode allows programs written with vector/SIMD multimedia extension instructions to produce floating-point results that are equivalent in precision to those written in the SPU instruction set. In this mode, as in the SPU environment, the default rounding mode is round to zero, denormals are treated as zero, and there are no infinities or NaNs.
The Cell Broadband Engine Programming Handbook has this to say on the subject: The first implementation of the Cell Broadband Engine Architecture (CBEA) (the CBE processor) supports instructions with a graphics rounding mode. This mode allows programs written with vector/SIMD multimedia extension instructions to produce floating-point results that are equivalent in precision to those written in the SPU instruction set. In this mode, as in the SPU environment, the default rounding mode is round to zero, denormals are treated as zero, and there are no infinities or NaNs.


This call change bit 12 (known as grap_md or grap_mode in various documents) in the HID1 register. Hardware Implementation Register 1 is a HV privileged resource, hence to change the mode from Supervisor mode requires a HV call.
To change this mode, bit 12 in the HID1 register (known as grap_md or grap_mode in various documents). HID1 is a HV privileged resource, hence to change the mode from Supervisor mode requires a HV call.


Reference Documents: Cell Broadband Engine Programming Handbook V1.1 Cell Broadband Engine Registers V1.5
Reference Documents: Cell Broadband Engine Programming Handbook V1.1 Cell Broadband Engine Registers V1.5
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When recompiled into Kernel module init function, accepts values of 0 and 1 for p1. All other values return -17 (LV1_ILLEGAL_PARAMETER_VALUE)
When recompiled into Kernel module init function, accepts values of 0 and 1 for p1. All other values return -17 (LV1_ILLEGAL_PARAMETER_VALUE)
----
----
=== lv1_set_thread_switch_control_register ===
=== lv1_set_thread_switch_control_register ===


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|-
|-
|R3
|R3
|status - 0 = OK, LV1_TYPE_MISMATCH when type is not 1. Other values are unknown but indicate failure.
|status
|-
|-
|R4
|R4
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|}
|}
----
----
=== lv1_write_remote_file ===
=== lv1_write_remote_file ===


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===== Kernel Call =====
===== Kernel Call =====


  result = lv1_allocate_device_dma_region( /*IN*/ bus_id, dev_id, io_size, io_pagesize, flag, /*OUT*/ &dma_region );
  result = lv1_allocate_device_dma_region( /*IN*/ bus_id, dev_id, io_size, io_pagesize, flag, &dma_region );


===== Parameters =====
===== Parameters =====
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Notes: When the device is little endian, the mode must be set to 8 bit for 8 bit DMA to work as expected, otherwise the bytes will be read/written in the wrong order. OTOH, this mode requires that 16 and 32-bit values are byte-swapped by the CPU since they will appear as little endian in memory.
Notes: When the device is little endian, the mode must be set to 8 bit for 8 bit DMA to work as expected, otherwise the bytes will be read/written in the wrong order. OTOH, this mode requires that 16 and 32-bit values are byte-swapped by the CPU since they will appear as little endian in memory.
----
----
=== lv1_free_device_dma_region ===
=== lv1_free_device_dma_region ===


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|R4
|R4
|IRQ Bitmap of all pending IRQ’s. This is a bitset.  
|IRQ Bitmap of all pending IRQ’s. This is a bitset.  
0 = IRQ not pending, 1 = IRQ pending.  
A bit = 0 means IRQ not pending, 1 = IRQ pending.  
Bit GPU_INTR_STATUS_VSYNC_0 = 0x01. IRQ for vsync on head A.
Bit GPU_INTR_STATUS_VSYNC_0 = 0. IRQ for vsync on head A. Unused by Kernel
Bit GPU_INTR_STATUS_VSYNC_1 = 0x02. IRQ for vsync on head B.
Bit GPU_INTR_STATUS_VSYNC_1 = 1. IRQ for vsync on head B. Used by Kernel
Bit GPU_INTR_UNK            = 0x04. Unknown, PS2 emulators panic when bit is set.
Bit GPU_INTR_STATUS_FLIP_0 = 2. IRQ for flip on head A. Unused by Kernel
Bit GPU_INTR_STATUS_FLIP_0 = 0x08. IRQ for flip on head A.
Bit GPU_INTR_STATUS_FLIP_1 = 3. IRQ for flip on head B. Unused by Kernel
Bit GPU_INTR_STATUS_FLIP_1 = 0x10. IRQ for flip on head B.
Bit GPU_INTR_STATUS_QUEUE_0 = 4. IRQ for queue on head A. Unused by Kernel
Bit GPU_INTR_STATUS_QUEUE_0 = 0x20. IRQ for queue on head A.
Bit GPU_INTR_STATUS_QUEUE_1 = 5. IRQ for queue on head B. Unused by Kernel
Bit GPU_INTR_STATUS_QUEUE_1 = 0x40. IRQ for queue on head B.
All bits are unused by kernel but used by PS2 emulators, additionally GPU_INTR_STATUS_VSYNC_1 and GPU_INTR_STATUS_FLIP_1 are used in Linux RSX driver.
|-
|-
|}
|}
----
----
=== lv1_gpu_attribute ===
=== lv1_gpu_attribute ===


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