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Proprietary 78-lines Interface with 54 testpads of the ''partial'' communication between [[South Bridge]] + [[Syscon Hardware]] with [[Starship2]] towards dual [[Flash (Hardware)|NAND]] 15pin (+ 2x VCC + 2x GND) interface.
Proprietary 78-lines Interface with 54 testpads of the ''partial'' communication between [[South Bridge]] + [[Syscon Hardware]] with [[Starship2]] towards dual [[Flash (Hardware)|NAND]] 15pin (+ 2x VCC + 2x GND) interface.


(in comparison, a [[Teensy 2.0++]] only has 51 lines, not all are useable as programmable I/O)
(in comparison, a Teensy 2.00++ only has 51 lines, not all are useable as programmable I/O)


The lower interface of NAND is exposed complete and also lesser wires/pins than the EBUS.
Because the exposed EBUS is only partial, entire flash will never be accessable, not even when the protocol is 100% reversed. The lower interface of NAND is exposed complete and also lesser wires/pins than the EBUS.


For this reason, reading/writing to flash is adviced using the <abbr title="Common Flash Interface">CFI</abbr> of the standardised dual [[Flash (Hardware)|NANDs]] (perfectly useable with a [[Teensy 2.0++]]).
For this reason, reading/writing to flash is adviced using the <abbr title="Common Flash Interface">CFI</abbr> of the standardised dual [[Flash (Hardware)|NANDs]] (perfectly useable with a Teensy 2.00++).


== Protocol / line usage ==
== Protocol / line usage ==
* Datastream:
* Datastream:
** 16 datalines
** 16 datalines
** 28 addresslines (only first 18 exposed)
** 28 addresslines
* Controllines:  
* Controllines:  
** 7x Chip Enable : CE0, CE1, CE2, CE3, CE4, CE5, CE6 (thus splitted into 7 virtual banks but only 3 exposed)
** 7x Chip Enable : CE0, CE1, CE2, CE3, CE4, CE5, cE6
** RBW : I/O R, I/O B, I/O W (only read exposed)
** RBW : I/O R, I/O B, I/O W
** 2x BWE (not exposed)
** 2x BWE
** SWE
** SWE
** Output Enable
** Output Enable
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** INT
** INT
* Other:
* Other:
** 3x MODlines (only 1 exposed)
** 3x MODlines
** 4x clocklines (only 1 exposed)
** 4x clocklines
** Tristate
** Tristate


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On {{DECR}} consoles with NAND, only 256 MB (1x 258MB) is used (although there is an empty TSOP pad for a second one).
On {{DECR}} consoles with NAND, only 256 MB (1x 258MB) is used (although there is an empty TSOP pad for a second one).


This points that the [[EBUS]] needs to address at least 512MB
'''See also:''' flash format , sb_rom_base and SS2_WORK inside [[lv0ldr]]


== Hardware lines / pads ==
== Hardware lines / pads ==
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! No. !! TP Name !! Usage !! COK-001 !! COK-002 !! SEM-001 !! Remark
! No. !! TP Name !! Usage !! COK-001 !! COK-002 !! SEM-001 !! Remark
|-
|-
| 0 || JL9300 || RESET || /SB_EBUS_RESET (PIO[7] / E1) || /SB_EBUS_RESET (/EBUSRESETZ / AL29) || /SB_EBUS_RESET (/EBUSRESETZ / P29) ||
| 0 || JL9300 || RESET || - || /SB_EBUS_RESET (/EBUSRESETZ / AL29)|| /SB_EBUS_RESET (/EBUSRESETZ / P29) ||
|-  
|-  
| 1 || JL9301 || MOD0 || /SB_MOD0 (MODZ0 / W8) || /SB_MOD0 (MODZ0 / J30) ||  ||
| 1 || JL9301 || MOD0 || /SB_MOD0 (MODZ0 / W8) || /SB_MOD0 (MODZ0 / J30) ||  ||
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| 69 || - || A27 || - (EBUSADDR[27] / H4) || - (EBUSADDR[27] / AL23) || - SB_EBUS_ADDR0 (EBUSADDR[27] / W27) || Not used
| 69 || - || A27 || - (EBUSADDR[27] / H4) || - (EBUSADDR[27] / AL23) || - SB_EBUS_ADDR0 (EBUSADDR[27] / W27) ||  
|-
|-
| 70 || - || A26 || - (EBUSADDR[26] / H3) || - (EBUSADDR[26] / AK23) || - SB_EBUS_ADDR0 (EBUSADDR[26] / W26) || Not used
| 70 || - || A26 || - (EBUSADDR[26] / H3) || - (EBUSADDR[26] / AK23) || - SB_EBUS_ADDR0 (EBUSADDR[26] / W26) ||  
|-
|-
| 71 || - || A25 || - (EBUSADDR[25] / V4) || - (EBUSADDR[25] / AC30) || - SB_EBUS_ADDR0 (EBUSADDR[25] / H26) || Not used
| 71 || - || A25 || - (EBUSADDR[25] / V4) || - (EBUSADDR[25] / AC30) || - SB_EBUS_ADDR0 (EBUSADDR[25] / H26) ||  
|-
|-
| 72 || - || A24 || - (EBUSADDR[24] / U2) || - (EBUSADDR[24] / AC29) || - SB_EBUS_ADDR0 (EBUSADDR[24] / H27) || Not used
| 72 || - || A24 || - (EBUSADDR[24] / U2) || - (EBUSADDR[24] / AC29) || - SB_EBUS_ADDR0 (EBUSADDR[24] / H27) ||  
|-
|-
| 73 || - || A23 || - (EBUSADDR[23] / U3) || - (EBUSADDR[23] / AC28) || - SB_EBUS_ADDR0 (EBUSADDR[23] / H29) || Not used
| 73 || - || A23 || - (EBUSADDR[23] / U3) || - (EBUSADDR[23] / AC28) || - SB_EBUS_ADDR0 (EBUSADDR[23] / H29) ||  
|-
|-
| 74 || - || A22 || - (EBUSADDR[22] / U1) || - (EBUSADDR[22] / AE29) || - SB_EBUS_ADDR0 (EBUSADDR[22] / H30) || Not used
| 74 || - || A22 || - (EBUSADDR[22] / U1) || - (EBUSADDR[22] / AE29) || - SB_EBUS_ADDR0 (EBUSADDR[22] / H30) ||  
|-
|-
| 75 || - || A21 || - (EBUSADDR[21] / M3) || - (EBUSADDR[21] / AJ29) || - SB_EBUS_ADDR0 (EBUSADDR[21] / P26) || Not used
| 75 || - || A21 || - (EBUSADDR[21] / M3) || - (EBUSADDR[21] / AJ29) || - SB_EBUS_ADDR0 (EBUSADDR[21] / P26) ||  
|-
|-
| 76 || - || A20 || - (EBUSADDR[20] / N1) || - (EBUSADDR[20] / AJ31) || - SB_EBUS_ADDR0 (EBUSADDR[20] / N27) || Not used
| 76 || - || A20 || - (EBUSADDR[20] / N1) || - (EBUSADDR[20] / AJ31) || - SB_EBUS_ADDR0 (EBUSADDR[20] / N27) ||  
|-
|-
| 77 || - || A19 || - (EBUSADDR[19] / N2) || - (EBUSADDR[19] / AH28) || - SB_EBUS_ADDR0 (EBUSADDR[19] / N26) || Not used
| 77 || - || A19 || - (EBUSADDR[19] / N2) || - (EBUSADDR[19] / AH28) || - SB_EBUS_ADDR0 (EBUSADDR[19] / N26) ||  
|-
|-
| 78 || - || A18 || - (EBUSADDR[18] / L4) || - (EBUSADDR[18] / AJ28) || - SB_EBUS_ADDR0 (EBUSADDR[18] / P27) || Not used
| 78 || - || A18 || - (EBUSADDR[18] / L4) || - (EBUSADDR[18] / AJ28) || - SB_EBUS_ADDR0 (EBUSADDR[18] / P27) ||  
|-
|-
| 21 || JL9321 || A17 || SB_EBUS_ADDR17 (EBUSADDR[17] / L3) || SB_EBUS_ADDR17 (EBUSADDR[17] / AH27) || SB_EBUS_ADDR0 (EBUSADDR[17] / P30) ||  
| 21 || JL9321 || A17 || SB_EBUS_ADDR17 (EBUSADDR[17] / L3) || SB_EBUS_ADDR17 (EBUSADDR[17] / AH27) || SB_EBUS_ADDR0 (EBUSADDR[17] / P30) ||  
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|-
|-
|}
|}
{{Motherboard Components}}<noinclude>[[Category:Main]]</noinclude>
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