Editing EBUS
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Latest revision | Your text | ||
Line 15: | Line 15: | ||
** 28 addresslines (only first 18 exposed) | ** 28 addresslines (only first 18 exposed) | ||
* Controllines: Β | * Controllines: Β | ||
** 7x Chip Enable : CE0, CE1, CE2, CE3, CE4, CE5, CE6 (thus splitted into 7 virtual | ** 7x Chip Enable : CE0, CE1, CE2, CE3, CE4, CE5, CE6 (thus splitted into 7 virtual banksm but only 3 exposed) | ||
** RBW : I/O R, I/O B, I/O W (only read exposed) | ** RBW : I/O R, I/O B, I/O W (only read exposed) | ||
** 2x BWE (not exposed) | ** 2x BWE (not exposed) |