Editing CXD9208GP

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! style="border-top:hidden; padding:0px; background-position:50%" | !! style="width:25px; min-width:25px; padding-right:0px" | Internal !! style="width:25px; min-width:25px; padding-right:0px" | External !! style="border-top:hidden; background-position:50%" | !! style="border-top:hidden; background-position:50%" |  
! style="border-top:hidden; padding:0px; background-position:50%" | !! style="width:25px; min-width:25px; padding-right:0px" | Internal !! style="width:25px; min-width:25px; padding-right:0px" | External !! style="border-top:hidden; background-position:50%" | !! style="border-top:hidden; background-position:50%" |  
|-
|-
| data-sort-value="A01" | A1 || {{cellcolors|#333|#fff}} TEST_IN_0 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="A01" | A1 || || || ||  
|-
|-
| data-sort-value="A02" | A2 || {{cellcolors|#333|#fff}} PLLAVS1 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="A02" | A2 || || || ||  
|-
|-
| data-sort-value="A03" | A3 || {{cellcolors|#8f8}} SIF_MSCLK || MSCLK || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pads B8 and A21
| data-sort-value="A03" | A3 || {{cellcolors|#8f8}} SIF_MSCLK || MSCLK || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pads B8 and A21
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| data-sort-value="C02" | C2 || {{cellcolors|#bbf}} PCI_AD29 || BC_PCI_AD29 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV31
| data-sort-value="C02" | C2 || {{cellcolors|#bbf}} PCI_AD29 || BC_PCI_AD29 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV31
|-
|-
| data-sort-value="C03" | C3 || {{cellcolors|#333|#fff}} TEST_IN_1 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="C03" | C3 || || || ||  
|-
|-
| data-sort-value="C04" | C4 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="C04" | C4 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
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| data-sort-value="E08" | E8 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="E08" | E8 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
|-
|-
| data-sort-value="E09" | E9 || {{cellcolors|#333|#fff}} TEST_IN_3 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="E09" | E9 || || || ||  
|-
|-
| data-sort-value="E10" | E10 || {{cellcolors|#f93|#fff}} VDD2 || +1.5V_EEGS_VDDO || {{pin}} || Connected to [[Regulators#Mitsumi_MM1561FFBE_.28500_mA_Noise_Reduction_Voltage_Regulator.29 | Mitsumi MM1561FFBE]] (IC6606) pin 1
| data-sort-value="E10" | E10 || {{cellcolors|#f93|#fff}} VDD2 || +1.5V_EEGS_VDDO || {{pin}} || Connected to [[Regulators#Mitsumi_MM1561FFBE_.28500_mA_Noise_Reduction_Voltage_Regulator.29 | Mitsumi MM1561FFBE]] (IC6606) pin 1
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| data-sort-value="E11" | E11 || {{cellcolors|#f93|#fff}} VDD2 || +1.5V_EEGS_VDDO || {{pin}} || Connected to [[Regulators#Mitsumi_MM1561FFBE_.28500_mA_Noise_Reduction_Voltage_Regulator.29 | Mitsumi MM1561FFBE]] (IC6606) pin 1
| data-sort-value="E11" | E11 || {{cellcolors|#f93|#fff}} VDD2 || +1.5V_EEGS_VDDO || {{pin}} || Connected to [[Regulators#Mitsumi_MM1561FFBE_.28500_mA_Noise_Reduction_Voltage_Regulator.29 | Mitsumi MM1561FFBE]] (IC6606) pin 1
|-
|-
| data-sort-value="E12" | E12 || {{cellcolors|#333|#fff}} TEST_IN_4 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="E12" | E12 || || || ||  
|-
|-
| data-sort-value="E13" | E13 || data-sort-value="SIF_AD08" {{cellcolors|#afa}} SIF_AD8 || data-sort-value="SIF_BC_AD08" | SIF_BC_AD8 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A16
| data-sort-value="E13" | E13 || data-sort-value="SIF_AD08" {{cellcolors|#afa}} SIF_AD8 || data-sort-value="SIF_BC_AD08" | SIF_BC_AD8 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A16
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| data-sort-value="F07" | F7 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="F07" | F7 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
|-
|-
| data-sort-value="F08" | F8 || {{cellcolors|#333|#fff}} TEST_IN_2 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="F08" | F8 || || || ||  
|-
|-
| data-sort-value="F09" | F9 || {{cellcolors|#c33|#fff}} VDDS || +3.3V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1593DFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1593DFBEG]] (IC6022) pin 1
| data-sort-value="F09" | F9 || {{cellcolors|#c33|#fff}} VDDS || +3.3V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1593DFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1593DFBEG]] (IC6022) pin 1
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| data-sort-value="H04" | H4 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
| data-sort-value="H04" | H4 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
|-
|-
| data-sort-value="H05" | H5 || {{cellcolors|#333|#fff}} TEST_PLL_BP_0 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="H05" | H5 || || || ||  
|-
|-
| data-sort-value="H06" | H6 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="H06" | H6 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
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| data-sort-value="K07" | K7 || {{cellcolors|#c33|#fff}} VDDS || +3.3V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1593DFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1593DFBEG]] (IC6022) pin 1
| data-sort-value="K07" | K7 || {{cellcolors|#c33|#fff}} VDDS || +3.3V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1593DFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1593DFBEG]] (IC6022) pin 1
|-
|-
| data-sort-value="K08" | K8 || {{cellcolors|#333|#fff}} TEST_PLL_BP_1 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="K08" | K8 || || || ||  
|-
|-
| data-sort-value="K09" | K9 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="K09" | K9 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
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| data-sort-value="P01" | P1 || {{cellcolors|#bbf}} PCI_AD12 || BC_PCI_AD12 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW23
| data-sort-value="P01" | P1 || {{cellcolors|#bbf}} PCI_AD12 || BC_PCI_AD12 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW23
|-
|-
| data-sort-value="P02" | P2 || {{cellcolors|#333|#fff}} PLLAVS0 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="P02" | P2 || || || ||  
|-
|-
| data-sort-value="P03" | P3 || {{cellcolors|#99f}} PCI_CLK || BC_PCI_CLK || {{pini}} || Connected to [[Timebases#ICS_ICS1493G-18LFT | ICS1493G-18LFT]] (IC5001) pin 5<br>Connected to [[South Bridge]] [[CXD2973GB]] pad AP28 through a 49.9 ohm resistor
| data-sort-value="P03" | P3 || {{cellcolors|#99f}} PCI_CLK || BC_PCI_CLK || {{pini}} || Connected to [[Timebases#ICS_ICS1493G-18LFT | ICS1493G-18LFT]] (IC5001) pin 5<br>Connected to [[South Bridge]] [[CXD2973GB]] pad AP28 through a 49.9 ohm resistor
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