Editing CELL BE
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! ABBR !! Usage !! Speed !! Notes | ! ABBR !! Usage !! Speed !! Notes | ||
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| BEI || Broadband engine interface || | | BEI || Broadband engine interface || || I/O Controller to FlexIO(/RSX) | ||
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| EIB || Element interconnect bus || 1.6GHz | | EIB || Element interconnect bus || 1.6GHz || used as communication ring for the 8 SPE (and PPU + MIC + BEI) | ||
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| FlexIO || High-speed I/O interface || | | FlexIO || High-speed I/O interface || || Flex I/O to [[RSX]] | ||
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| L2 || Level 2 cache || 3.2GHz | | L2 || Level 2 cache || 3.2GHz || 512KB L2 cache for PPE | ||
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| MIC || Memory interface controller || | | MIC || Memory interface controller || || Memory controller to XIO(/Rambus XDR) | ||
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| MBL || MIC bus logic || | | MBL || MIC bus logic || || From MIC(/PPE) to EIB(/SPE's) | ||
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| PPE || Power processor element || 3.2GHz | | PPE || Power processor element || 3.2GHz || Main dualthreaded CPU | ||
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| SPE || Synergistic processor element || <span title="see SPU table below">3.2GHz/1.6GHz</span> || 8 present, 1 disabled from factory | | SPE || Synergistic processor element || <span title="see SPU table below">3.2GHz/1.6GHz</span> || 8 present, 1 disabled from factory | ||
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| XIO || Extreme data rate I/O cell || | | XIO || Extreme data rate I/O cell || || Rambus XDR Interface | ||
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| TEST || Test control unit | | TEST || Test control unit/pervasive logic || || Used for preboot, selfcheck (and secureboot?) | ||
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| PLL || Phase-Locked Loop || 400MHz || Before preboot external clock (400MHz) is used (see [[Timebases]])<br />afterwards only internal PLL | | PLL || Phase-Locked Loop || 400MHz || Before preboot external clock (400MHz) is used (see [[Timebases]])<br />afterwards only internal PLL for main clocks | ||
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! ABBR !! Usage !! Speed !! Notes | ! ABBR !! Usage !! Speed !! Notes | ||
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| BIU || Bus interface unit || 1.6GHz | | BIU || Bus interface unit || 1.6GHz || connects DMAC+EIB and LS+EIB | ||
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| DMAC || Direct memory access controller || 1.6GHz | | DMAC || Direct memory access controller || 1.6GHz || controls DMA, SPU+LS and BIU(/EIB) | ||
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| EIB || Element interconnect bus || 1.6GHz | | EIB || Element interconnect bus || 1.6GHz || busring to which all SPE's are connected (and PPU + MIC + BEI) | ||
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| LS || Local store || 3.2GHz | | LS || Local store || 3.2GHz || 256KB of local memory, accessable via DMA/MBOX | ||
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| MFC || Memory flow controller || 1.6GHz | | MFC || Memory flow controller || 1.6GHz || | ||
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| MIC || Memory interface controller || | | MIC || Memory interface controller || || Memory controller to XIO(/Rambus XDR) | ||
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| MMIO || Memory-mapped I/O || 1.6GHz | | MMIO || Memory-mapped I/O || 1.6GHz || | ||
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| MMU || Memory management unit || 1.6GHz | | MMU || Memory management unit || 1.6GHz || used by DMAC for management | ||
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| SPU || Synergistic processor unit || 3.2GHz | | SPU || Synergistic processor unit || 3.2GHz || SPU execution unit | ||
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| TLB || Translation lookaside buffer || 1.6GHz | | TLB || Translation lookaside buffer || 1.6GHz || used by MMU as buffer | ||
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|} | |} | ||