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[[Category:Hardware]] | |||
= Cell Broadband Engine = | |||
= Cell Broadband Engine | <div style="float:right">[[File:CellBE.jpg|200px|thumb|left|Cell Broadband Engine<br />CPU with heatplate<br />CXD2992AGB]]<br />[[File:CXD2992AGB 46J2494 diemrk1.jpg|200px|thumb|left|IBM markings in CXD2992AGB die]]</div> | ||
The Cell CPU has one 3.2Ghz PPE (Power Processor Element) with two threads and eight 3.2Ghz SPE (Synergistic Processing Elements). | The Cell CPU has one 3.2Ghz PPE (Power Processor Element) with two threads and eight 3.2Ghz SPE (Synergistic Processing Elements). | ||
The PPE is a general purpose CPU, while the eight SPE are geared towards processing data in parallel. One SPE is disabled to increase yield, so the PS3 can have at most 9 threads | The PPE is a general purpose CPU, while the eight SPE are geared towards processing data in parallel. One SPE is disabled to increase yield, so the PS3 can have at most 9 threads runnings at the same time (2 from PPE and 7 from SPE). Note that one SPE is reserved for the hypervisor, so PS3 programs can take advantage of 8 threads. Both the PPE and SPE of the Cell are 64 bit, and manipulate data in Big Endian. | ||
== Specifications == | == Specifications == | ||
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== Die explained == | == Die explained == | ||
< | <table width="100%" align="left"><tr> | ||
File:CELLBE die large.jpg|Cell Broadband Engine<br />Die - 90nm | <td align="left">[[File:CELLBE die large.jpg|200px|thumb|left|Cell Broadband Engine<br />Die - 90nm]]</td> | ||
File:SPU-DIE.PNG|Cell Broadband Engine<br />SPU Die map | <td align="left">[[File:SPU-DIE.PNG|140px|thumb|left|Cell Broadband Engine<br />SPU Die map]]</td> | ||
File:CellBE-map-90nm.jpg|Cell Broadband Engine<br />Die map - 90nm | <td align="left">[[File:CellBE-map-90nm.jpg|200px|thumb|left|Cell Broadband Engine<br />Die map - 90nm]]</td> | ||
File:CellBE-map-65nm.jpg|Cell Broadband Engine<br />Die map - 65nm | <td align="left">[[File:CellBE-map-65nm.jpg|200px|thumb|left|Cell Broadband Engine<br />Die map - 65nm]]</td> | ||
File:CellBE-map-45nm.jpg|Cell Broadband Engine<br />Die map - 45nm | <td align="left">[[File:CellBE-map-45nm.jpg|200px|thumb|left|Cell Broadband Engine<br />Die map - 45nm]]</td> | ||
</tr></table> | |||
</ | |||
<div style="float:right">[[File:Cell-90nm-die.png|200px|thumb|left|CellBE 90nm die]]</div> | |||
{| border="1" cellspacing="0" cellpadding="5" border="#999" class="wikitable" style="border:1px solid #999; border-collapse: collapse;" | {| border="1" cellspacing="0" cellpadding="5" border="#999" class="wikitable" style="border:1px solid #999; border-collapse: collapse;" | ||
|- bgcolor="#cccccc" | |- bgcolor="#cccccc" | ||
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=== SPE === | === SPE === | ||
<div style="float:right">[[File:SPU-diagram-DMA.png|200px|thumb|left|CellBE - SPU diagram]]</div> | |||
{| border="1" cellspacing="0" cellpadding="5" border="#999" class="wikitable" style="border:1px solid #999; border-collapse: collapse;" | {| border="1" cellspacing="0" cellpadding="5" border="#999" class="wikitable" style="border:1px solid #999; border-collapse: collapse;" | ||
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Reference: http://hpc.pnl.gov/people/fabrizio/papers/ieeemicro-cell.pdf // backup/mirror: [http://www.multiupload.com/UN7VJHHER1 ieeemicro-cell.pdf (222.51 KB)] | Reference: http://hpc.pnl.gov/people/fabrizio/papers/ieeemicro-cell.pdf // backup/mirror: [http://www.multiupload.com/UN7VJHHER1 ieeemicro-cell.pdf (222.51 KB)] | ||
== | == Bandwith I/O == | ||
<div style="float:right">[[File:Cellbe-bandwith.gif|200px|thumb|left|CellBE bandwidth]]</div> | <div style="float:right">[[File:Cellbe-bandwith.gif|200px|thumb|left|CellBE bandwidth]]</div> | ||
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Reference: [http://www.ibm.com/developerworks/power/library/pa-cellperf/ Cell Broadband Engine Architecture and its first implementation - A performance view] | Reference: [http://www.ibm.com/developerworks/power/library/pa-cellperf/ Cell Broadband Engine Architecture and its first implementation - A performance view] | ||
== Serial Numbers @ SKU == | |||
The Cell BE was introduced at 90nm. Later, PS3 model numbers starting with CECHG uses the 65nm version, while the PS3 Slim (CECH-20xx) used the 45nm version (See [[SKU Models]] and table below). | The Cell BE was introduced at 90nm. Later, PS3 model numbers starting with CECHG uses the 65nm version, while the PS3 Slim (CECH-20xx) used the 45nm version (See [[SKU Models]] and table below). | ||
A sampling of the | A sampling of the serial numbers by model number. | ||
{| border="1" cellspacing="0" cellpadding="5" border="#999" class="wikitable" style="border:1px solid #999; border-collapse: collapse;" | {| border="1" cellspacing="0" cellpadding="5" border="#999" class="wikitable" style="border:1px solid #999; border-collapse: collapse;" | ||
|- bgcolor="#cccccc" | |- bgcolor="#cccccc" | ||
! PS3 Model !! Mobo Model !! Mobo | ! PS3 Model !! Mobo Model !! Mobo serial !! CELL Serial !! Die Tech !! Total Die Size !! Width x Length !! SPU size !! PPE Size !! Remark | ||
|- | |- | ||
| [[CECHAxx]] || [[COK-00x#COK-001|COK-001]] || - || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets] | | [[CECHAxx]] || [[COK-00x#COK-001|COK-001]] || - || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets] | ||
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|- | |- | ||
| [[CECHCxx]] || [[COK-00x#COK-002|COK-002]] || 1-873-513-21<br />1-873-513-31 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets] | | [[CECHCxx]] || [[COK-00x#COK-002|COK-002]] || 1-873-513-21<br />1-873-513-31 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets] | ||
|- | |||
| style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">[[CECHDxx]]</span> || colspan="9" style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">SKU never released</span> | |||
|- | |- | ||
| [[CECHExx]] || [[COK-00x#COK-002W|COK-002W]] || - || CXD29?? || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets] | | [[CECHExx]] || [[COK-00x#COK-002W|COK-002W]] || - || CXD29?? || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets] | ||
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|- | |- | ||
| [[CECHExx]] || [[COK-00x#COK-002W|COK-002W]] || 1-873-513-31 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&t=2131 reballing.es] | | [[CECHExx]] || [[COK-00x#COK-002W|COK-002W]] || 1-873-513-31 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&t=2131 reballing.es] | ||
|- | |||
| style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">[[CECHFxx]]</span> || colspan="9" style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">SKU never released</span> | |||
|- | |- | ||
| [[CECHGxx]] || [[SEM-00x|SEM-001]] || 1-875-384-11<br />1-875-384-21<br />1-875-384-31 || [[CXD2981AGB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets] | | [[CECHGxx]] || [[SEM-00x|SEM-001]] || 1-875-384-11<br />1-875-384-21<br />1-875-384-31 || [[CXD2981AGB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets] | ||
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| [[CECHHxx]] || [[DIA-00x#DIA-001|DIA-001]] || 1-875-938-31 || [[CXD2981AGB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://reballing.es/viewtopic.php?f=13&t=2131 reballing.es] | | [[CECHHxx]] || [[DIA-00x#DIA-001|DIA-001]] || 1-875-938-31 || [[CXD2981AGB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://reballing.es/viewtopic.php?f=13&t=2131 reballing.es] | ||
|- | |- | ||
| [[CECHJxx]] || [[DIA-00x#DIA-002|DIA-002]] || 1-876-912-31 || [[ | | style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">[[CECHIxx]]</span> || colspan="9" style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">SKU never released</span> | ||
|- | |||
| [[CECHJxx]] || [[DIA-00x#DIA-002|DIA-002]] || 1-876-912-31 || [[CXD2981GB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets] | |||
|- | |- | ||
| [[CECHKxx]] || [[DIA-00x#DIA-002|DIA-002]] || 1-876-912-32 || [[CXD2989AGB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets] | | [[CECHKxx]] || [[DIA-00x#DIA-002|DIA-002]] || 1-876-912-32 || [[CXD2989AGB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets] | ||
|- | |- | ||
| [[CECHLxx]] || [[VER-00x|VER-001]] || - || [[CXD2990AGB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets] | | [[CECHLxx]] || [[VER-00x|VER-001]] || - || [[CXD2990AGB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets] | ||
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| [[CECHMxx]] || [[VER-00x|VER-001]] || ?1-878-196-41? || -? || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || -? | | [[CECHMxx]] || [[VER-00x|VER-001]] || ?1-878-196-41? || -? || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || -? | ||
|- | |- | ||
| [[CECHPxx]] || [[VER-00x|VER-001]] || 1-878-196- | | style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">[[CECHNxx]]</span> || colspan="9" style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">SKU never released</span> | ||
|- | |||
| style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">[[CECHOxx]]</span> || colspan="9" style="text-align:center; background-color:lightgrey;" | <span style="background-color:lightgrey;">SKU never released</span> | |||
|- | |||
| [[CECHPxx]] || [[VER-00x|VER-001]] || ?1-878-196-41? || -? || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || -? | |||
|- | |- | ||
| [[CECHQxx]] || [[VER-00x|VER-001]] || ?1-878-196-41? || CXD299? || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets] | | [[CECHQxx]] || [[VER-00x|VER-001]] || ?1-878-196-41? || CXD299? || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets] | ||
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|- | |- | ||
| [[CECH-21xx]] || [[SUR-00x|SUR-001]] || 1-881-945-11 || [[CXD2992AGB]] || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || [http://reballing.es/viewtopic.php?f=13&t=2131 reballing.es] | | [[CECH-21xx]] || [[SUR-00x|SUR-001]] || 1-881-945-11 || [[CXD2992AGB]] || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || [http://reballing.es/viewtopic.php?f=13&t=2131 reballing.es] | ||
|- | |- | ||
| [[CECH-25xx]] || [[JTP-00x|JTP-001]] || 1-882-481-31 || [[CXD2992GB]] || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets] | | [[CECH-25xx]] || [[JTP-00x|JTP-001]] || 1-882-481-31 || [[CXD2992GB]] || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets] | ||
|- | |- | ||
| [[CECH-25xx]] || [[JSD-00x|JSD-001]] || 1-882- | | [[CECH-25xx]] || [[JSD-00x|JSD-001]] || 1-882-481-31 || [[CXD2992GB]]? || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || | ||
|- | |- | ||
| [[CECH-30xx]] || [[KTE-00x|KTE-001]] || 1-884-749-11 || [[CXD2996GB]]? || 45nm? || 115.46mm²? || 12.75mm x 9.06mm? || 6.47mm²? || 11.32mm²? || -? | | [[CECH-30xx]] || [[KTE-00x|KTE-001]] || 1-884-749-11 || [[CXD2996GB]]? || 45nm? || 115.46mm²? || 12.75mm x 9.06mm? || 6.47mm²? || 11.32mm²? || -? | ||
|- | |- | ||
| [[CECH-40xx]] || [[MSX-00x|MSX-001]] || 1-886-928-11 || [[CXD2996BGB]] || 45nm? || 115.46mm²? || 12.75mm x 9.06mm? || 6.47mm²? || 11.32mm²? || -? | |||
| [[CECH-40xx]] || [[MSX-00x|MSX-001]] || 1-886-928-11 || [[CXD2996BGB]] || 45nm? || 115.46mm²? || 12.75mm x 9.06mm? || 6.47mm²? || 11.32mm²? || | |||
|- | |- | ||
| [[CECH-40xx]] || [[MPX-00x|MPX-001]] || 1-887-233-11 || [[CXD2996BGB]] || 45nm? || 115.46mm²? || 12.75mm x 9.06mm? || 6.47mm²? || 11.32mm²? || -? | | [[CECH-40xx]] || [[MPX-00x|MPX-001]] || 1-887-233-11 || [[CXD2996BGB]] || 45nm? || 115.46mm²? || 12.75mm x 9.06mm? || 6.47mm²? || 11.32mm²? || -? | ||
|- | |- | ||
|} | |} | ||
===Alternative listing=== | |||
===Alternative | * [[CECHAxx]]/[[COK-00x#COK-001|COK-001]], [[CECHBxx]]/[[COK-00x#COK-001|COK-001]] and [[CECHCxx]]/[[COK-00x#COK-002|COK-002]] : [[CXD2964AGB]] (CELL 90nm) | ||
* [[CECHAxx]]/[[COK-00x#COK-001|COK-001]] : [[CXD2964GB]] (CELL 90nm) | |||
* [[CECHGxx]]/[[SEM-00x|SEM-001]] and [[CECHHxx]]/[[DIA-00x#DIA-001|DIA-001]] : [[CXD2981AGB]] (CELL 65nm) | |||
* [[CECHJxx]]/[[DIA-00x#DIA-002|DIA-002]] and [[CECHKxx]]/[[DIA-00x#DIA-002|DIA-002]] : [[CXD2989]] (CELL 65nm) | |||
* | * [[CECHLxx]]/[[VER-00x|VER-001]] up and including [[CECHQxx]]/[[VER-00x|VER-001]] : [[CXD2990ABG]] (CELL 65nm) | ||
* [[CECH-20xx]]/[[DYN-00x|DYN-001]], [[CECH-21xx]]/[[SUR-00x|SUR-001]], [[CECH-25xx]]/[[JTP-00x|JTP-001]] and [[CECH-25xx]]/[[JTP-00x|JTP-001]] : [[CXD2992AGB]] (CELL 45nm) | |||
* [[CECH-30xx]]/[[KTE-00x|KTE-001]] : [[CXD2996GB]] (CELL 45nm) | |||
* [[CECH-40xx]]/[[MSX-00x|MSX-001]] : [[CXD2996GB]] (CELL 45nm) | |||
* | |||
* | |||
<br /> | <br /> | ||
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unsigned int pvr; | unsigned int pvr; | ||
__asm__ __volatile__ (" | __asm__ __volatile__ ("mfspr %0, 287" : "=r" (pvr)); | ||
code above | code above works in ring 0 only. | ||
{| border="1" cellspacing="0" cellpadding="5" border="#999" class="wikitable sortable" style="border:1px solid #999; border-collapse: collapse;" | {| border="1" cellspacing="0" cellpadding="5" border="#999" class="wikitable sortable" style="border:1px solid #999; border-collapse: collapse;" | ||
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|- | |- | ||
| [[CXD2996GB]] || 45nm || || | | [[CXD2996GB]] || 45nm || || | ||
|- | |- | ||
|} | |} | ||
=== Cell Revisions === | === Cell Revisions === | ||
{| border="1" cellspacing="0" cellpadding="5" border="#999" class="wikitable sortable" style="border:1px solid #999; border-collapse: collapse;" | {| border="1" cellspacing="0" cellpadding="5" border="#999" class="wikitable sortable" style="border:1px solid #999; border-collapse: collapse;" | ||
|- bgcolor="#cccccc" | |- bgcolor="#cccccc" | ||
! CellBE Version !! PVR | ! CellBE Version !! PVR | ||
|- | |- | ||
| Cell/BE v1.0 || 0x0070 0x0100 | | Cell/BE v1.0 || 0x0070 0x0100 | ||
|- | |- | ||
| Cell/BE v2.0 || 0x0070 0x0400 | | Cell/BE v2.0 || 0x0070 0x0400 | ||
|- | |- | ||
| Cell/BE v3.0 || 0x0070 0x0500 | | Cell/BE v3.0 || 0x0070 0x0500 | ||
|- | |- | ||
| Cell/BE v3.1 || 0x0070 0x0501 | | Cell/BE v3.1 || 0x0070 0x0501 | ||
|- | |- | ||
| Cell/BE v3.2 || 0x0070 0x0501 | | Cell/BE v3.2 || 0x0070 0x0501 | ||
|- | |- | ||
| ???? || 0x0070 0x2100 | | ???? || 0x0070 0x2100 | ||
|- | |- | ||
|} | |} | ||
== Unsorted == | == Unsorted == | ||
Integrated Heat Spreader (IHS) removed pic's: | |||
* when it goes OK: http://imageshack.us/f/855/imgp0048v.jpg/ http://imageshack.us/f/850/imgp0046i.jpg/ | |||
* when it goes wrong: http://postimage.org/image/hl11y3969/full/ | |||
{{Console}} | |||
[[Category:CELL BE]] |