http://www.psdevwiki.com/ps3/api.php?action=feedcontributions&user=114.34.113.113&feedformat=atom PS3 Developer wiki - User contributions [en] 2024-03-28T12:00:19Z User contributions MediaWiki 1.39.6 http://www.psdevwiki.com/ps3/index.php?title=CELL_BE&diff=26876 CELL BE 2014-02-12T20:15:16Z <p>114.34.113.113: Change CECH-42xx CELL Serial from CXD2996BGB to CXD2999AGG</p> <hr /> <div>= Cell Broadband Engine =<br /> <br /> &lt;div style=&quot;float:right&quot;&gt;[[File:CellBE.jpg|200px|thumb|left|Cell Broadband Engine&lt;br /&gt;CPU with heatplate&lt;br /&gt;CXD2992AGB]]&lt;br /&gt;[[File:CXD2992AGB 46J2494 diemrk1.jpg|200px|thumb|left|IBM markings in CXD2992AGB die]]&lt;/div&gt;<br /> <br /> The Cell CPU has one 3.2Ghz PPE (Power Processor Element) with two threads and eight 3.2Ghz SPE (Synergistic Processing Elements).<br /> <br /> The PPE is a general purpose CPU, while the eight SPE are geared towards processing data in parallel. One SPE is disabled to increase yield, so the PS3 can have at most 9 threads runnings at the same time (2 from PPE and 7 from SPE). Note that one SPE is reserved for the hypervisor, so PS3 programs can take advantage of 8 threads. Both the PPE and SPE of the Cell are 64 bit, and manipulate data in Big Endian.<br /> <br /> == Specifications ==<br /> <br /> * 1 PPE (Power Processor Element)<br /> ** 3.2Ghz<br /> ** 64 bit, Big Endian<br /> ** 2 threads (can run at same time)<br /> ** L1 cache: 32kB data + 32kB instruction<br /> ** L2 cache: 512kB<br /> ** Memory bus width: 64bit (serial)<br /> ** VMX (Altivec) instruction set support<br /> ** Full IEEE-754 compliant <br /> ** the PPU can execute two double precision or eight single precision operations per clockcycle<br /> * 8 SPE (Synergistic Processing Element)<br /> ** 3.2Ghz<br /> ** 64 bit, Big Endian<br /> ** 1 SPE disabled to improve chip yield (see: [[Unlocking the 8th SPE]])<br /> ** 1 SPE dedicated for hypervisor security<br /> ** 256KB local store per SPE<br /> ** 128 registers per SPE<br /> ** Dual Issue (Each SPE can execute 2 instructions per clock)<br /> ** IEEE-754 compliant in double precision (single precision round-towards-zero instead of round-towards-even)<br /> <br /> There is a lot of info about CELL/BE on the [[Cell Programming IBM]] page.<br /> <br /> == Die explained ==<br /> &lt;table width=&quot;100%&quot; align=&quot;left&quot;&gt;&lt;tr&gt;<br /> &lt;td align=&quot;left&quot;&gt;[[File:CELLBE die large.jpg|200px|thumb|left|Cell Broadband Engine&lt;br /&gt;Die - 90nm]]&lt;/td&gt;<br /> &lt;td align=&quot;left&quot;&gt;[[File:SPU-DIE.PNG|140px|thumb|left|Cell Broadband Engine&lt;br /&gt;SPU Die map]]&lt;/td&gt;<br /> &lt;td align=&quot;left&quot;&gt;[[File:CellBE-map-90nm.jpg|200px|thumb|left|Cell Broadband Engine&lt;br /&gt;Die map - 90nm]]&lt;/td&gt;<br /> &lt;td align=&quot;left&quot;&gt;[[File:CellBE-map-65nm.jpg|200px|thumb|left|Cell Broadband Engine&lt;br /&gt;Die map - 65nm]]&lt;/td&gt;<br /> &lt;td align=&quot;left&quot;&gt;[[File:CellBE-map-45nm.jpg|200px|thumb|left|Cell Broadband Engine&lt;br /&gt;Die map - 45nm]]&lt;/td&gt;<br /> &lt;/tr&gt;&lt;/table&gt;<br /> <br /> &lt;div style=&quot;float:right&quot;&gt;[[File:Cell-90nm-die.png|200px|thumb|left|CellBE 90nm die]]&lt;/div&gt;<br /> {| border=&quot;1&quot; cellspacing=&quot;0&quot; cellpadding=&quot;5&quot; border=&quot;#999&quot; class=&quot;wikitable&quot; style=&quot;border:1px solid #999; border-collapse: collapse;&quot; <br /> |- bgcolor=&quot;#cccccc&quot;<br /> ! ABBR !! Usage !! Speed !! Notes<br /> |-<br /> | BEI || Broadband engine interface || 1.6GHz (NCLK/2) || I/O Controller to FlexIO(/RSX)<br /> |-<br /> | EIB || Element interconnect bus || 1.6GHz (NCLK/2) || used as communication ring for the 8 SPE (and PPU + MIC + BEI)<br /> |-<br /> | FlexIO || High-speed I/O interface || 2.5Ghz (RC_REFCLK : 500MHz 1:5 PLL) || Flex I/O to [[RSX]]<br /> |-<br /> | L2 || Level 2 cache || 3.2GHz (NCLK) || 512KB L2 cache for PPE<br /> |-<br /> | MIC || Memory interface controller || 1.6GHz (NCLK/2) || Memory controller to XIO(/Rambus XDR)<br /> |-<br /> | MBL || MIC bus logic || 1.6GHz (NCLK/2) || From MIC(/PPE) to EIB(/SPE's)<br /> |-<br /> | PPE || Power processor element || 3.2GHz (NCLK) || Main dualthreaded CPU<br /> |-<br /> | SPE || Synergistic processor element || &lt;span title=&quot;see SPU table below&quot;&gt;3.2GHz/1.6GHz&lt;/span&gt; || 8 present, 1 disabled from factory<br /> |-<br /> | XIO || Extreme data rate I/O cell || 1.6GHz (Y0_RQ_CTM/Y1_RQ_CTM : 400MHz 1:4 PLL) || Rambus XDR Interface<br /> |-<br /> | TEST || Test control unit (TCU) / pervasive logic (PRV) || || Used for power management, thermal management, clock control, software-performance monitoring, trace analysis, preboot (and secureboot?), &lt;br /&gt;also has RAS-unit (Reliability, Availability, Serviceability), JTAG (IEEE 1149 test access port) and SPI Serial Peripheral Interface<br /> |-<br /> | PLL || Phase-Locked Loop || 400MHz || Before preboot external clock (400MHz) is used (see [[Timebases]])&lt;br /&gt;afterwards only internal PLL (PLL_REFCLK : 400MHz 1:8 PLL) for main clocks: NCLK=3.2GHz, NCLK/2=1.6GHz, MiClk=1.6GHz, XIO Clk=1.6GHz, BClk=1.667GHz, RO/TO Clk=2.5GHz<br /> |-<br /> |}<br /> <br /> === SPE ===<br /> &lt;div style=&quot;float:right&quot;&gt;[[File:SPU-diagram-DMA.png|200px|thumb|left|CellBE - SPU diagram]]&lt;/div&gt;<br /> <br /> {| border=&quot;1&quot; cellspacing=&quot;0&quot; cellpadding=&quot;5&quot; border=&quot;#999&quot; class=&quot;wikitable&quot; style=&quot;border:1px solid #999; border-collapse: collapse;&quot; <br /> |- bgcolor=&quot;#cccccc&quot;<br /> ! ABBR !! Usage !! Speed !! Notes<br /> |-<br /> | BIU || Bus interface unit || 1.6GHz (NCLK/2) || connects DMAC+EIB and LS+EIB<br /> |-<br /> | DMAC || Direct memory access controller || 1.6GHz (NCLK/2) || controls DMA, SPU+LS and BIU(/EIB)<br /> |-<br /> | EIB || Element interconnect bus || 1.6GHz (NCLK/2) || busring to which all SPE's are connected (and PPU + MIC + BEI)<br /> |-<br /> | LS || Local store || 3.2GHz (NCLK) || 256KB of local memory, accessable via DMA/MBOX<br /> |-<br /> | MFC || Memory flow controller || 1.6GHz (NCLK/2) || <br /> |-<br /> | MIC || Memory interface controller || 1.6GHz (NCLK/2) || Memory controller to XIO(/Rambus XDR)<br /> |-<br /> | MMIO || Memory-mapped I/O || 1.6GHz (NCLK/2) || <br /> |-<br /> | MMU || Memory management unit || 1.6GHz (NCLK/2) || used by DMAC for management<br /> |-<br /> | SPU || Synergistic processor unit || 3.2GHz (NCLK) || SPU execution unit<br /> |-<br /> | TLB || Translation lookaside buffer || 1.6GHz (NCLK/2) || used by MMU as buffer<br /> |-<br /> |}<br /> <br /> Reference: http://hpc.pnl.gov/people/fabrizio/papers/ieeemicro-cell.pdf // backup/mirror: [http://www.multiupload.com/UN7VJHHER1 ieeemicro-cell.pdf (222.51 KB)]<br /> <br /> == Bandwith I/O ==<br /> &lt;div style=&quot;float:right&quot;&gt;[[File:Cellbe-bandwith.gif|200px|thumb|left|CellBE bandwidth]]&lt;/div&gt;<br /> <br /> * MIC (Memory Interface Controller) &amp;lt;from/to&amp;gt; [[RAM#Main_System_Memory|dual Rambus XDR]]: 25.6GB/s theoretical<br /> <br /> * IOIF0 (I/O Interface to RSX): 20GB/s to&amp;gt; [[RSX]] / 15 GB/s &amp;lt; [[RSX]] ([[RSX]] &amp;lt;from/to&amp;gt; [[RAM#Graphics_Memory|GDDR3]]: 20.8GB/s @ 650MHz)<br /> <br /> * IOIF1 (I/O Interface to Southbridge): &amp;lt;from/to&amp;gt; [[South Bridge]] : 2.5GB/s <br /> <br /> * EIB (Element Interconnect Bus) : 4x 128bit buses / 128byte packets : 204.8 GB/s total<br /> <br /> * PPU (PowerPC Processing Element) : 25.6 GLOP/s FPU, L1/L2: 51.2GB/s<br /> <br /> * LHS (Load Hit Store) pipeline stall : ~40 clockcycles<br /> <br /> * SPE (Synergistic Processor Elements) : 2 IPC SPU to Local Store : 51.2GB/s<br /> <br /> Reference: [http://www.ibm.com/developerworks/power/library/pa-cellperf/ Cell Broadband Engine Architecture and its first implementation - A performance view]<br /> <br /> <br /> == Serial Numbers @ SKU ==<br /> The Cell BE was introduced at 90nm. Later, PS3 model numbers starting with CECHG uses the 65nm version, while the PS3 Slim (CECH-20xx) used the 45nm version (See [[SKU Models]] and table below).<br /> <br /> A sampling of the serial numbers by model number.<br /> {| border=&quot;1&quot; cellspacing=&quot;0&quot; cellpadding=&quot;5&quot; border=&quot;#999&quot; class=&quot;wikitable&quot; style=&quot;border:1px solid #999; border-collapse: collapse;&quot; <br /> |- bgcolor=&quot;#cccccc&quot;<br /> ! PS3 Model !! Mobo Model !! Mobo serial !! CELL Serial !! Die Tech !! Total Die Size !! Width x Length !! SPU size !! PPE Size !! Remark<br /> |-<br /> | [[CECHAxx]] || [[COK-00x#COK-001|COK-001]] || - || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHAxx]] || [[COK-00x#COK-001|COK-001]] || 1-871-868-12 || [[CXD2964AGB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHAxx]] || [[COK-00x#COK-001|COK-001]] || 1-871-868-22 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHAxx]] || [[COK-00x#COK-001|COK-001]] || 1-871-868-32 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHBxx]] || [[COK-00x#COK-001|COK-001]] || - || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHBxx]] || [[COK-00x#COK-001|COK-001]] || 1-871-868-22 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHBxx]] || [[COK-00x#COK-001|COK-001]] || 1-871-868-32 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHCxx]] || [[COK-00x#COK-002|COK-002]] || 1-873-513-21&lt;br /&gt;1-873-513-31 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;[[CECHDxx]]&lt;/span&gt; || colspan=&quot;9&quot; style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;SKU never released&lt;/span&gt;<br /> |-<br /> | [[CECHExx]] || [[COK-00x#COK-002W|COK-002W]] || - || CXD29?? || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHExx]] || [[COK-00x#COK-002W|COK-002W]] || 1-873-513-21 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHExx]] || [[COK-00x#COK-002W|COK-002W]] || 1-873-513-21 || [[CXD2964AGB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHExx]] || [[COK-00x#COK-002W|COK-002W]] || 1-873-513-31 || [[CXD2964AGB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHExx]] || [[COK-00x#COK-002W|COK-002W]] || 1-873-513-31 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;[[CECHFxx]]&lt;/span&gt; || colspan=&quot;9&quot; style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;SKU never released&lt;/span&gt;<br /> |-<br /> | [[CECHGxx]] || [[SEM-00x|SEM-001]] || 1-875-384-11&lt;br /&gt;1-875-384-21&lt;br /&gt;1-875-384-31 || [[CXD2981AGB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHHxx]] || [[DIA-00x#DIA-001|DIA-001]] || 1-875-368-11&lt;br /&gt;1-875-368-31 || [[CXD2981GB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHHxx]] || [[DIA-00x#DIA-001|DIA-001]] || 1-875-938-11 || [[CXD2981AGB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHHxx]] || [[DIA-00x#DIA-001|DIA-001]] || 1-875-938-31 || [[CXD2981AGB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;[[CECHIxx]]&lt;/span&gt; || colspan=&quot;9&quot; style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;SKU never released&lt;/span&gt;<br /> |-<br /> | [[CECHJxx]] || [[DIA-00x#DIA-002|DIA-002]] || 1-876-912-31 || [[CXD2981GB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHKxx]] || [[DIA-00x#DIA-002|DIA-002]] || 1-876-912-32 || [[CXD2989AGB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHLxx]] || [[VER-00x|VER-001]] || - || [[CXD2990AGB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHLxx]] || [[VER-00x|VER-001]] || 1-878-196-31 || [[CXD2990GB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHMxx]] || [[VER-00x|VER-001]] || ?1-878-196-41? || -? || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || -?<br /> |-<br /> | style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;[[CECHNxx]]&lt;/span&gt; || colspan=&quot;9&quot; style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;SKU never released&lt;/span&gt;<br /> |-<br /> | style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;[[CECHOxx]]&lt;/span&gt; || colspan=&quot;9&quot; style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;SKU never released&lt;/span&gt;<br /> |-<br /> | [[CECHPxx]] || [[VER-00x|VER-001]] || ?1-878-196-41? || -? || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || -?<br /> |-<br /> | [[CECHQxx]] || [[VER-00x|VER-001]] || ?1-878-196-41? || CXD299? || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECH-20xx]] || [[DYN-00x|DYN-001]] || - || [[CXD2992AGB]] || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECH-20xx]] || [[DYN-00x|DYN-001]] || 1-880-055-31 || [[CXD2992AGB]] || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECH-21xx]] || [[SUR-00x|SUR-001]] || - || [[CXD2992AGB]] || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECH-21xx]] || [[SUR-00x|SUR-001]] || 1-881-945-11 || [[CXD2992AGB]] || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECH-25xx]] || [[JTP-00x|JTP-001]] || 1-882-481-31 || [[CXD2992GB]] || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECH-25xx]] || [[JSD-00x|JSD-001]] || 1-882-481-31 || [[CXD2992GB]]? || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || <br /> |-<br /> | [[CECH-30xx]] || [[KTE-00x|KTE-001]] || 1-884-749-11 || [[CXD2996GB]]? || 45nm? || 115.46mm²? || 12.75mm x 9.06mm? || 6.47mm²? || 11.32mm²? || -?<br /> |-<br /> | [[CECH-40xx]] || [[MSX-00x|MSX-001]] || 1-886-928-11 || [[CXD2996BGB]] || 45nm? || 115.46mm²? || 12.75mm x 9.06mm? || 6.47mm²? || 11.32mm²? || -?<br /> |-<br /> | [[CECH-40xx]] || [[MPX-00x|MPX-001]] || 1-887-233-11 || [[CXD2996BGB]] || 45nm? || 115.46mm²? || 12.75mm x 9.06mm? || 6.47mm²? || 11.32mm²? || -?<br /> |-<br /> | [[CECH-42xx]] || [[PQX-00x|PQX-001]] || 1-888-629-22 || [[CXD2999AGG]] || ?nm || ?mm² || ?mm x ?mm || ?mm² || ?mm² || [http://www.mobile01.com/topicdetail.php?f=281&amp;t=3747667&amp;p=1 mobile01_tw]<br /> |-<br /> |}<br /> ===Alternative listing===<br /> * [[CECHAxx]]/[[COK-00x#COK-001|COK-001]], [[CECHBxx]]/[[COK-00x#COK-001|COK-001]] and [[CECHCxx]]/[[COK-00x#COK-002|COK-002]] : [[CXD2964AGB]] (CELL 90nm)<br /> * [[CECHAxx]]/[[COK-00x#COK-001|COK-001]] : [[CXD2964GB]] (CELL 90nm)<br /> * [[CECHGxx]]/[[SEM-00x|SEM-001]] and [[CECHHxx]]/[[DIA-00x#DIA-001|DIA-001]] : [[CXD2981AGB]] (CELL 65nm)<br /> * [[CECHJxx]]/[[DIA-00x#DIA-002|DIA-002]] and [[CECHKxx]]/[[DIA-00x#DIA-002|DIA-002]] : [[CXD2989]] (CELL 65nm)<br /> * [[CECHLxx]]/[[VER-00x|VER-001]] up and including [[CECHQxx]]/[[VER-00x|VER-001]] : [[CXD2990ABG]] (CELL 65nm)<br /> * [[CECH-20xx]]/[[DYN-00x|DYN-001]], [[CECH-21xx]]/[[SUR-00x|SUR-001]], [[CECH-25xx]]/[[JTP-00x|JTP-001]] and [[CECH-25xx]]/[[JTP-00x|JTP-001]] : [[CXD2992AGB]] (CELL 45nm)<br /> * [[CECH-30xx]]/[[KTE-00x|KTE-001]] : [[CXD2996GB]] (CELL 45nm)<br /> * [[CECH-40xx]]/[[MSX-00x|MSX-001]] : [[CXD2996GB]] (CELL 45nm)<br /> * [[CECH-42xx]]/[[PQX-00x|PQX-001]] : [[CXD2999AGG]] (CELL ?nm)<br /> &lt;br /&gt;<br /> <br /> == PVR (powerpc version register) ==<br /> The PVR inside the microprocessor is the only way to identify what version of what part you have.<br /> <br /> cat /proc/cpuinfo<br /> <br /> or<br /> <br /> unsigned int pvr;<br /> __asm__ __volatile__ (&quot;mfpvr %0&quot; : &quot;=r&quot; (pvr));<br /> <br /> code above should work in kernel &amp; user mode. &lt;!-- http://lists.freebsd.org/pipermail/svn-src-head/2010-February/014780.html --&gt;<br /> <br /> {| border=&quot;1&quot; cellspacing=&quot;0&quot; cellpadding=&quot;5&quot; border=&quot;#999&quot; class=&quot;wikitable sortable&quot; style=&quot;border:1px solid #999; border-collapse: collapse;&quot; <br /> |- bgcolor=&quot;#cccccc&quot;<br /> ! CellBE serial !! die tech !! PVR !! Notes<br /> |-<br /> | [[CXD2964AGB]] || 90nm || || <br /> |-<br /> | [[CXD2964GB]] || 90nm || || <br /> |-<br /> | [[CXD2981AGB]] || 65nm || || <br /> |-<br /> | [[CXD2981GB]] || 65nm || || <br /> |-<br /> | [[CXD2989AGB]] || 65nm || || <br /> |-<br /> | [[CXD2989GB]] || 65nm || || <br /> |-<br /> | [[CXD2990AGB]] || 65nm || || <br /> |-<br /> | [[CXD2990GB]] || 65nm || || <br /> |-<br /> | [[CXD2992AGB]] || 45nm || || <br /> |-<br /> | [[CXD2992GB]] || 45nm || || <br /> |-<br /> | [[CXD2996GB]] || 45nm || || <br /> |-<br /> | [[CXD2999AGG]] || || || <br /> |-<br /> |}<br /> <br /> === Cell Revisions ===<br /> <br /> {| border=&quot;1&quot; cellspacing=&quot;0&quot; cellpadding=&quot;5&quot; border=&quot;#999&quot; class=&quot;wikitable sortable&quot; style=&quot;border:1px solid #999; border-collapse: collapse;&quot; <br /> |- bgcolor=&quot;#cccccc&quot;<br /> ! CellBE Version !! PVR !! Speed<br /> |-<br /> | Cell/BE v1.0 || 0x0070 0x0100 || 2.4GHz<br /> |-<br /> | Cell/BE v2.0 || 0x0070 0x0400 || 2.4GHz<br /> |-<br /> | Cell/BE v3.0 || 0x0070 0x0500 || 3.2GHz<br /> |-<br /> | Cell/BE v3.1 || 0x0070 0x0501 || 3.2GHz<br /> |-<br /> | Cell/BE v3.2 || 0x0070 0x0501 || 3.2GHz<br /> |-<br /> | ???? || 0x0070 0x2100 || <br /> |-<br /> |}<br /> <br /> == Unsorted ==<br /> === Integrated Heat Spreader (IHS) removed pic's ===<br /> <br /> * when it goes OK: http://imageshack.us/f/855/imgp0048v.jpg/ http://imageshack.us/f/850/imgp0046i.jpg/<br /> <br /> * when it goes wrong: http://postimage.org/image/hl11y3969/full/ http://postimage.org/image/bbydh5s6v/full/<br /> <br /> === IHS size and mounting ===<br /> on a COK-001 the CPU heatspreader is 4.00cm x 4.00cm while the RSX heatspreader is 4.25cm x 4.25 cm - CPU and RSX mountholes are 8.75cm apart and 6.3mm diameter<br /> <br /> although a PC cooler should fit within these dimensions fine, mounting the 2 (which are also elevated differently from the motherboard) can be problematic<br /> <br /> <br /> <br /> {{Motherboard Components}}&lt;noinclude&gt;[[Category:Main]]&lt;/noinclude&gt;</div> 114.34.113.113 http://www.psdevwiki.com/ps3/index.php?title=CELL_BE&diff=26875 CELL BE 2014-02-12T20:11:44Z <p>114.34.113.113: Change CECH-42xx SPU size from 6.47mm² to unsure</p> <hr /> <div>= Cell Broadband Engine =<br /> <br /> &lt;div style=&quot;float:right&quot;&gt;[[File:CellBE.jpg|200px|thumb|left|Cell Broadband Engine&lt;br /&gt;CPU with heatplate&lt;br /&gt;CXD2992AGB]]&lt;br /&gt;[[File:CXD2992AGB 46J2494 diemrk1.jpg|200px|thumb|left|IBM markings in CXD2992AGB die]]&lt;/div&gt;<br /> <br /> The Cell CPU has one 3.2Ghz PPE (Power Processor Element) with two threads and eight 3.2Ghz SPE (Synergistic Processing Elements).<br /> <br /> The PPE is a general purpose CPU, while the eight SPE are geared towards processing data in parallel. One SPE is disabled to increase yield, so the PS3 can have at most 9 threads runnings at the same time (2 from PPE and 7 from SPE). Note that one SPE is reserved for the hypervisor, so PS3 programs can take advantage of 8 threads. Both the PPE and SPE of the Cell are 64 bit, and manipulate data in Big Endian.<br /> <br /> == Specifications ==<br /> <br /> * 1 PPE (Power Processor Element)<br /> ** 3.2Ghz<br /> ** 64 bit, Big Endian<br /> ** 2 threads (can run at same time)<br /> ** L1 cache: 32kB data + 32kB instruction<br /> ** L2 cache: 512kB<br /> ** Memory bus width: 64bit (serial)<br /> ** VMX (Altivec) instruction set support<br /> ** Full IEEE-754 compliant <br /> ** the PPU can execute two double precision or eight single precision operations per clockcycle<br /> * 8 SPE (Synergistic Processing Element)<br /> ** 3.2Ghz<br /> ** 64 bit, Big Endian<br /> ** 1 SPE disabled to improve chip yield (see: [[Unlocking the 8th SPE]])<br /> ** 1 SPE dedicated for hypervisor security<br /> ** 256KB local store per SPE<br /> ** 128 registers per SPE<br /> ** Dual Issue (Each SPE can execute 2 instructions per clock)<br /> ** IEEE-754 compliant in double precision (single precision round-towards-zero instead of round-towards-even)<br /> <br /> There is a lot of info about CELL/BE on the [[Cell Programming IBM]] page.<br /> <br /> == Die explained ==<br /> &lt;table width=&quot;100%&quot; align=&quot;left&quot;&gt;&lt;tr&gt;<br /> &lt;td align=&quot;left&quot;&gt;[[File:CELLBE die large.jpg|200px|thumb|left|Cell Broadband Engine&lt;br /&gt;Die - 90nm]]&lt;/td&gt;<br /> &lt;td align=&quot;left&quot;&gt;[[File:SPU-DIE.PNG|140px|thumb|left|Cell Broadband Engine&lt;br /&gt;SPU Die map]]&lt;/td&gt;<br /> &lt;td align=&quot;left&quot;&gt;[[File:CellBE-map-90nm.jpg|200px|thumb|left|Cell Broadband Engine&lt;br /&gt;Die map - 90nm]]&lt;/td&gt;<br /> &lt;td align=&quot;left&quot;&gt;[[File:CellBE-map-65nm.jpg|200px|thumb|left|Cell Broadband Engine&lt;br /&gt;Die map - 65nm]]&lt;/td&gt;<br /> &lt;td align=&quot;left&quot;&gt;[[File:CellBE-map-45nm.jpg|200px|thumb|left|Cell Broadband Engine&lt;br /&gt;Die map - 45nm]]&lt;/td&gt;<br /> &lt;/tr&gt;&lt;/table&gt;<br /> <br /> &lt;div style=&quot;float:right&quot;&gt;[[File:Cell-90nm-die.png|200px|thumb|left|CellBE 90nm die]]&lt;/div&gt;<br /> {| border=&quot;1&quot; cellspacing=&quot;0&quot; cellpadding=&quot;5&quot; border=&quot;#999&quot; class=&quot;wikitable&quot; style=&quot;border:1px solid #999; border-collapse: collapse;&quot; <br /> |- bgcolor=&quot;#cccccc&quot;<br /> ! ABBR !! Usage !! Speed !! Notes<br /> |-<br /> | BEI || Broadband engine interface || 1.6GHz (NCLK/2) || I/O Controller to FlexIO(/RSX)<br /> |-<br /> | EIB || Element interconnect bus || 1.6GHz (NCLK/2) || used as communication ring for the 8 SPE (and PPU + MIC + BEI)<br /> |-<br /> | FlexIO || High-speed I/O interface || 2.5Ghz (RC_REFCLK : 500MHz 1:5 PLL) || Flex I/O to [[RSX]]<br /> |-<br /> | L2 || Level 2 cache || 3.2GHz (NCLK) || 512KB L2 cache for PPE<br /> |-<br /> | MIC || Memory interface controller || 1.6GHz (NCLK/2) || Memory controller to XIO(/Rambus XDR)<br /> |-<br /> | MBL || MIC bus logic || 1.6GHz (NCLK/2) || From MIC(/PPE) to EIB(/SPE's)<br /> |-<br /> | PPE || Power processor element || 3.2GHz (NCLK) || Main dualthreaded CPU<br /> |-<br /> | SPE || Synergistic processor element || &lt;span title=&quot;see SPU table below&quot;&gt;3.2GHz/1.6GHz&lt;/span&gt; || 8 present, 1 disabled from factory<br /> |-<br /> | XIO || Extreme data rate I/O cell || 1.6GHz (Y0_RQ_CTM/Y1_RQ_CTM : 400MHz 1:4 PLL) || Rambus XDR Interface<br /> |-<br /> | TEST || Test control unit (TCU) / pervasive logic (PRV) || || Used for power management, thermal management, clock control, software-performance monitoring, trace analysis, preboot (and secureboot?), &lt;br /&gt;also has RAS-unit (Reliability, Availability, Serviceability), JTAG (IEEE 1149 test access port) and SPI Serial Peripheral Interface<br /> |-<br /> | PLL || Phase-Locked Loop || 400MHz || Before preboot external clock (400MHz) is used (see [[Timebases]])&lt;br /&gt;afterwards only internal PLL (PLL_REFCLK : 400MHz 1:8 PLL) for main clocks: NCLK=3.2GHz, NCLK/2=1.6GHz, MiClk=1.6GHz, XIO Clk=1.6GHz, BClk=1.667GHz, RO/TO Clk=2.5GHz<br /> |-<br /> |}<br /> <br /> === SPE ===<br /> &lt;div style=&quot;float:right&quot;&gt;[[File:SPU-diagram-DMA.png|200px|thumb|left|CellBE - SPU diagram]]&lt;/div&gt;<br /> <br /> {| border=&quot;1&quot; cellspacing=&quot;0&quot; cellpadding=&quot;5&quot; border=&quot;#999&quot; class=&quot;wikitable&quot; style=&quot;border:1px solid #999; border-collapse: collapse;&quot; <br /> |- bgcolor=&quot;#cccccc&quot;<br /> ! ABBR !! Usage !! Speed !! Notes<br /> |-<br /> | BIU || Bus interface unit || 1.6GHz (NCLK/2) || connects DMAC+EIB and LS+EIB<br /> |-<br /> | DMAC || Direct memory access controller || 1.6GHz (NCLK/2) || controls DMA, SPU+LS and BIU(/EIB)<br /> |-<br /> | EIB || Element interconnect bus || 1.6GHz (NCLK/2) || busring to which all SPE's are connected (and PPU + MIC + BEI)<br /> |-<br /> | LS || Local store || 3.2GHz (NCLK) || 256KB of local memory, accessable via DMA/MBOX<br /> |-<br /> | MFC || Memory flow controller || 1.6GHz (NCLK/2) || <br /> |-<br /> | MIC || Memory interface controller || 1.6GHz (NCLK/2) || Memory controller to XIO(/Rambus XDR)<br /> |-<br /> | MMIO || Memory-mapped I/O || 1.6GHz (NCLK/2) || <br /> |-<br /> | MMU || Memory management unit || 1.6GHz (NCLK/2) || used by DMAC for management<br /> |-<br /> | SPU || Synergistic processor unit || 3.2GHz (NCLK) || SPU execution unit<br /> |-<br /> | TLB || Translation lookaside buffer || 1.6GHz (NCLK/2) || used by MMU as buffer<br /> |-<br /> |}<br /> <br /> Reference: http://hpc.pnl.gov/people/fabrizio/papers/ieeemicro-cell.pdf // backup/mirror: [http://www.multiupload.com/UN7VJHHER1 ieeemicro-cell.pdf (222.51 KB)]<br /> <br /> == Bandwith I/O ==<br /> &lt;div style=&quot;float:right&quot;&gt;[[File:Cellbe-bandwith.gif|200px|thumb|left|CellBE bandwidth]]&lt;/div&gt;<br /> <br /> * MIC (Memory Interface Controller) &amp;lt;from/to&amp;gt; [[RAM#Main_System_Memory|dual Rambus XDR]]: 25.6GB/s theoretical<br /> <br /> * IOIF0 (I/O Interface to RSX): 20GB/s to&amp;gt; [[RSX]] / 15 GB/s &amp;lt; [[RSX]] ([[RSX]] &amp;lt;from/to&amp;gt; [[RAM#Graphics_Memory|GDDR3]]: 20.8GB/s @ 650MHz)<br /> <br /> * IOIF1 (I/O Interface to Southbridge): &amp;lt;from/to&amp;gt; [[South Bridge]] : 2.5GB/s <br /> <br /> * EIB (Element Interconnect Bus) : 4x 128bit buses / 128byte packets : 204.8 GB/s total<br /> <br /> * PPU (PowerPC Processing Element) : 25.6 GLOP/s FPU, L1/L2: 51.2GB/s<br /> <br /> * LHS (Load Hit Store) pipeline stall : ~40 clockcycles<br /> <br /> * SPE (Synergistic Processor Elements) : 2 IPC SPU to Local Store : 51.2GB/s<br /> <br /> Reference: [http://www.ibm.com/developerworks/power/library/pa-cellperf/ Cell Broadband Engine Architecture and its first implementation - A performance view]<br /> <br /> <br /> == Serial Numbers @ SKU ==<br /> The Cell BE was introduced at 90nm. Later, PS3 model numbers starting with CECHG uses the 65nm version, while the PS3 Slim (CECH-20xx) used the 45nm version (See [[SKU Models]] and table below).<br /> <br /> A sampling of the serial numbers by model number.<br /> {| border=&quot;1&quot; cellspacing=&quot;0&quot; cellpadding=&quot;5&quot; border=&quot;#999&quot; class=&quot;wikitable&quot; style=&quot;border:1px solid #999; border-collapse: collapse;&quot; <br /> |- bgcolor=&quot;#cccccc&quot;<br /> ! PS3 Model !! Mobo Model !! Mobo serial !! CELL Serial !! Die Tech !! Total Die Size !! Width x Length !! SPU size !! PPE Size !! Remark<br /> |-<br /> | [[CECHAxx]] || [[COK-00x#COK-001|COK-001]] || - || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHAxx]] || [[COK-00x#COK-001|COK-001]] || 1-871-868-12 || [[CXD2964AGB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHAxx]] || [[COK-00x#COK-001|COK-001]] || 1-871-868-22 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHAxx]] || [[COK-00x#COK-001|COK-001]] || 1-871-868-32 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHBxx]] || [[COK-00x#COK-001|COK-001]] || - || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHBxx]] || [[COK-00x#COK-001|COK-001]] || 1-871-868-22 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHBxx]] || [[COK-00x#COK-001|COK-001]] || 1-871-868-32 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHCxx]] || [[COK-00x#COK-002|COK-002]] || 1-873-513-21&lt;br /&gt;1-873-513-31 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;[[CECHDxx]]&lt;/span&gt; || colspan=&quot;9&quot; style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;SKU never released&lt;/span&gt;<br /> |-<br /> | [[CECHExx]] || [[COK-00x#COK-002W|COK-002W]] || - || CXD29?? || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHExx]] || [[COK-00x#COK-002W|COK-002W]] || 1-873-513-21 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHExx]] || [[COK-00x#COK-002W|COK-002W]] || 1-873-513-21 || [[CXD2964AGB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHExx]] || [[COK-00x#COK-002W|COK-002W]] || 1-873-513-31 || [[CXD2964AGB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHExx]] || [[COK-00x#COK-002W|COK-002W]] || 1-873-513-31 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;[[CECHFxx]]&lt;/span&gt; || colspan=&quot;9&quot; style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;SKU never released&lt;/span&gt;<br /> |-<br /> | [[CECHGxx]] || [[SEM-00x|SEM-001]] || 1-875-384-11&lt;br /&gt;1-875-384-21&lt;br /&gt;1-875-384-31 || [[CXD2981AGB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHHxx]] || [[DIA-00x#DIA-001|DIA-001]] || 1-875-368-11&lt;br /&gt;1-875-368-31 || [[CXD2981GB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHHxx]] || [[DIA-00x#DIA-001|DIA-001]] || 1-875-938-11 || [[CXD2981AGB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHHxx]] || [[DIA-00x#DIA-001|DIA-001]] || 1-875-938-31 || [[CXD2981AGB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;[[CECHIxx]]&lt;/span&gt; || colspan=&quot;9&quot; style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;SKU never released&lt;/span&gt;<br /> |-<br /> | [[CECHJxx]] || [[DIA-00x#DIA-002|DIA-002]] || 1-876-912-31 || [[CXD2981GB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHKxx]] || [[DIA-00x#DIA-002|DIA-002]] || 1-876-912-32 || [[CXD2989AGB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHLxx]] || [[VER-00x|VER-001]] || - || [[CXD2990AGB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHLxx]] || [[VER-00x|VER-001]] || 1-878-196-31 || [[CXD2990GB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHMxx]] || [[VER-00x|VER-001]] || ?1-878-196-41? || -? || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || -?<br /> |-<br /> | style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;[[CECHNxx]]&lt;/span&gt; || colspan=&quot;9&quot; style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;SKU never released&lt;/span&gt;<br /> |-<br /> | style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;[[CECHOxx]]&lt;/span&gt; || colspan=&quot;9&quot; style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;SKU never released&lt;/span&gt;<br /> |-<br /> | [[CECHPxx]] || [[VER-00x|VER-001]] || ?1-878-196-41? || -? || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || -?<br /> |-<br /> | [[CECHQxx]] || [[VER-00x|VER-001]] || ?1-878-196-41? || CXD299? || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECH-20xx]] || [[DYN-00x|DYN-001]] || - || [[CXD2992AGB]] || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECH-20xx]] || [[DYN-00x|DYN-001]] || 1-880-055-31 || [[CXD2992AGB]] || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECH-21xx]] || [[SUR-00x|SUR-001]] || - || [[CXD2992AGB]] || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECH-21xx]] || [[SUR-00x|SUR-001]] || 1-881-945-11 || [[CXD2992AGB]] || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECH-25xx]] || [[JTP-00x|JTP-001]] || 1-882-481-31 || [[CXD2992GB]] || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECH-25xx]] || [[JSD-00x|JSD-001]] || 1-882-481-31 || [[CXD2992GB]]? || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || <br /> |-<br /> | [[CECH-30xx]] || [[KTE-00x|KTE-001]] || 1-884-749-11 || [[CXD2996GB]]? || 45nm? || 115.46mm²? || 12.75mm x 9.06mm? || 6.47mm²? || 11.32mm²? || -?<br /> |-<br /> | [[CECH-40xx]] || [[MSX-00x|MSX-001]] || 1-886-928-11 || [[CXD2996BGB]] || 45nm? || 115.46mm²? || 12.75mm x 9.06mm? || 6.47mm²? || 11.32mm²? || -?<br /> |-<br /> | [[CECH-40xx]] || [[MPX-00x|MPX-001]] || 1-887-233-11 || [[CXD2996BGB]] || 45nm? || 115.46mm²? || 12.75mm x 9.06mm? || 6.47mm²? || 11.32mm²? || -?<br /> |-<br /> | [[CECH-42xx]] || [[PQX-00x|PQX-001]] || 1-888-629-22 || [[CXD2996BGB]] || ?nm || ?mm² || ?mm x ?mm || ?mm² || ?mm² || [http://www.mobile01.com/topicdetail.php?f=281&amp;t=3747667&amp;p=1 mobile01_tw]<br /> |-<br /> |}<br /> ===Alternative listing===<br /> * [[CECHAxx]]/[[COK-00x#COK-001|COK-001]], [[CECHBxx]]/[[COK-00x#COK-001|COK-001]] and [[CECHCxx]]/[[COK-00x#COK-002|COK-002]] : [[CXD2964AGB]] (CELL 90nm)<br /> * [[CECHAxx]]/[[COK-00x#COK-001|COK-001]] : [[CXD2964GB]] (CELL 90nm)<br /> * [[CECHGxx]]/[[SEM-00x|SEM-001]] and [[CECHHxx]]/[[DIA-00x#DIA-001|DIA-001]] : [[CXD2981AGB]] (CELL 65nm)<br /> * [[CECHJxx]]/[[DIA-00x#DIA-002|DIA-002]] and [[CECHKxx]]/[[DIA-00x#DIA-002|DIA-002]] : [[CXD2989]] (CELL 65nm)<br /> * [[CECHLxx]]/[[VER-00x|VER-001]] up and including [[CECHQxx]]/[[VER-00x|VER-001]] : [[CXD2990ABG]] (CELL 65nm)<br /> * [[CECH-20xx]]/[[DYN-00x|DYN-001]], [[CECH-21xx]]/[[SUR-00x|SUR-001]], [[CECH-25xx]]/[[JTP-00x|JTP-001]] and [[CECH-25xx]]/[[JTP-00x|JTP-001]] : [[CXD2992AGB]] (CELL 45nm)<br /> * [[CECH-30xx]]/[[KTE-00x|KTE-001]] : [[CXD2996GB]] (CELL 45nm)<br /> * [[CECH-40xx]]/[[MSX-00x|MSX-001]] : [[CXD2996GB]] (CELL 45nm)<br /> * [[CECH-42xx]]/[[PQX-00x|PQX-001]] : [[CXD2999AGG]] (CELL ?nm)<br /> &lt;br /&gt;<br /> <br /> == PVR (powerpc version register) ==<br /> The PVR inside the microprocessor is the only way to identify what version of what part you have.<br /> <br /> cat /proc/cpuinfo<br /> <br /> or<br /> <br /> unsigned int pvr;<br /> __asm__ __volatile__ (&quot;mfpvr %0&quot; : &quot;=r&quot; (pvr));<br /> <br /> code above should work in kernel &amp; user mode. &lt;!-- http://lists.freebsd.org/pipermail/svn-src-head/2010-February/014780.html --&gt;<br /> <br /> {| border=&quot;1&quot; cellspacing=&quot;0&quot; cellpadding=&quot;5&quot; border=&quot;#999&quot; class=&quot;wikitable sortable&quot; style=&quot;border:1px solid #999; border-collapse: collapse;&quot; <br /> |- bgcolor=&quot;#cccccc&quot;<br /> ! CellBE serial !! die tech !! PVR !! Notes<br /> |-<br /> | [[CXD2964AGB]] || 90nm || || <br /> |-<br /> | [[CXD2964GB]] || 90nm || || <br /> |-<br /> | [[CXD2981AGB]] || 65nm || || <br /> |-<br /> | [[CXD2981GB]] || 65nm || || <br /> |-<br /> | [[CXD2989AGB]] || 65nm || || <br /> |-<br /> | [[CXD2989GB]] || 65nm || || <br /> |-<br /> | [[CXD2990AGB]] || 65nm || || <br /> |-<br /> | [[CXD2990GB]] || 65nm || || <br /> |-<br /> | [[CXD2992AGB]] || 45nm || || <br /> |-<br /> | [[CXD2992GB]] || 45nm || || <br /> |-<br /> | [[CXD2996GB]] || 45nm || || <br /> |-<br /> | [[CXD2999AGG]] || || || <br /> |-<br /> |}<br /> <br /> === Cell Revisions ===<br /> <br /> {| border=&quot;1&quot; cellspacing=&quot;0&quot; cellpadding=&quot;5&quot; border=&quot;#999&quot; class=&quot;wikitable sortable&quot; style=&quot;border:1px solid #999; border-collapse: collapse;&quot; <br /> |- bgcolor=&quot;#cccccc&quot;<br /> ! CellBE Version !! PVR !! Speed<br /> |-<br /> | Cell/BE v1.0 || 0x0070 0x0100 || 2.4GHz<br /> |-<br /> | Cell/BE v2.0 || 0x0070 0x0400 || 2.4GHz<br /> |-<br /> | Cell/BE v3.0 || 0x0070 0x0500 || 3.2GHz<br /> |-<br /> | Cell/BE v3.1 || 0x0070 0x0501 || 3.2GHz<br /> |-<br /> | Cell/BE v3.2 || 0x0070 0x0501 || 3.2GHz<br /> |-<br /> | ???? || 0x0070 0x2100 || <br /> |-<br /> |}<br /> <br /> == Unsorted ==<br /> === Integrated Heat Spreader (IHS) removed pic's ===<br /> <br /> * when it goes OK: http://imageshack.us/f/855/imgp0048v.jpg/ http://imageshack.us/f/850/imgp0046i.jpg/<br /> <br /> * when it goes wrong: http://postimage.org/image/hl11y3969/full/ http://postimage.org/image/bbydh5s6v/full/<br /> <br /> === IHS size and mounting ===<br /> on a COK-001 the CPU heatspreader is 4.00cm x 4.00cm while the RSX heatspreader is 4.25cm x 4.25 cm - CPU and RSX mountholes are 8.75cm apart and 6.3mm diameter<br /> <br /> although a PC cooler should fit within these dimensions fine, mounting the 2 (which are also elevated differently from the motherboard) can be problematic<br /> <br /> <br /> <br /> {{Motherboard Components}}&lt;noinclude&gt;[[Category:Main]]&lt;/noinclude&gt;</div> 114.34.113.113 http://www.psdevwiki.com/ps3/index.php?title=CELL_BE&diff=26874 CELL BE 2014-02-12T20:04:14Z <p>114.34.113.113: Add CECH-42xx Serial Numbers @ SKU</p> <hr /> <div>= Cell Broadband Engine =<br /> <br /> &lt;div style=&quot;float:right&quot;&gt;[[File:CellBE.jpg|200px|thumb|left|Cell Broadband Engine&lt;br /&gt;CPU with heatplate&lt;br /&gt;CXD2992AGB]]&lt;br /&gt;[[File:CXD2992AGB 46J2494 diemrk1.jpg|200px|thumb|left|IBM markings in CXD2992AGB die]]&lt;/div&gt;<br /> <br /> The Cell CPU has one 3.2Ghz PPE (Power Processor Element) with two threads and eight 3.2Ghz SPE (Synergistic Processing Elements).<br /> <br /> The PPE is a general purpose CPU, while the eight SPE are geared towards processing data in parallel. One SPE is disabled to increase yield, so the PS3 can have at most 9 threads runnings at the same time (2 from PPE and 7 from SPE). Note that one SPE is reserved for the hypervisor, so PS3 programs can take advantage of 8 threads. Both the PPE and SPE of the Cell are 64 bit, and manipulate data in Big Endian.<br /> <br /> == Specifications ==<br /> <br /> * 1 PPE (Power Processor Element)<br /> ** 3.2Ghz<br /> ** 64 bit, Big Endian<br /> ** 2 threads (can run at same time)<br /> ** L1 cache: 32kB data + 32kB instruction<br /> ** L2 cache: 512kB<br /> ** Memory bus width: 64bit (serial)<br /> ** VMX (Altivec) instruction set support<br /> ** Full IEEE-754 compliant <br /> ** the PPU can execute two double precision or eight single precision operations per clockcycle<br /> * 8 SPE (Synergistic Processing Element)<br /> ** 3.2Ghz<br /> ** 64 bit, Big Endian<br /> ** 1 SPE disabled to improve chip yield (see: [[Unlocking the 8th SPE]])<br /> ** 1 SPE dedicated for hypervisor security<br /> ** 256KB local store per SPE<br /> ** 128 registers per SPE<br /> ** Dual Issue (Each SPE can execute 2 instructions per clock)<br /> ** IEEE-754 compliant in double precision (single precision round-towards-zero instead of round-towards-even)<br /> <br /> There is a lot of info about CELL/BE on the [[Cell Programming IBM]] page.<br /> <br /> == Die explained ==<br /> &lt;table width=&quot;100%&quot; align=&quot;left&quot;&gt;&lt;tr&gt;<br /> &lt;td align=&quot;left&quot;&gt;[[File:CELLBE die large.jpg|200px|thumb|left|Cell Broadband Engine&lt;br /&gt;Die - 90nm]]&lt;/td&gt;<br /> &lt;td align=&quot;left&quot;&gt;[[File:SPU-DIE.PNG|140px|thumb|left|Cell Broadband Engine&lt;br /&gt;SPU Die map]]&lt;/td&gt;<br /> &lt;td align=&quot;left&quot;&gt;[[File:CellBE-map-90nm.jpg|200px|thumb|left|Cell Broadband Engine&lt;br /&gt;Die map - 90nm]]&lt;/td&gt;<br /> &lt;td align=&quot;left&quot;&gt;[[File:CellBE-map-65nm.jpg|200px|thumb|left|Cell Broadband Engine&lt;br /&gt;Die map - 65nm]]&lt;/td&gt;<br /> &lt;td align=&quot;left&quot;&gt;[[File:CellBE-map-45nm.jpg|200px|thumb|left|Cell Broadband Engine&lt;br /&gt;Die map - 45nm]]&lt;/td&gt;<br /> &lt;/tr&gt;&lt;/table&gt;<br /> <br /> &lt;div style=&quot;float:right&quot;&gt;[[File:Cell-90nm-die.png|200px|thumb|left|CellBE 90nm die]]&lt;/div&gt;<br /> {| border=&quot;1&quot; cellspacing=&quot;0&quot; cellpadding=&quot;5&quot; border=&quot;#999&quot; class=&quot;wikitable&quot; style=&quot;border:1px solid #999; border-collapse: collapse;&quot; <br /> |- bgcolor=&quot;#cccccc&quot;<br /> ! ABBR !! Usage !! Speed !! Notes<br /> |-<br /> | BEI || Broadband engine interface || 1.6GHz (NCLK/2) || I/O Controller to FlexIO(/RSX)<br /> |-<br /> | EIB || Element interconnect bus || 1.6GHz (NCLK/2) || used as communication ring for the 8 SPE (and PPU + MIC + BEI)<br /> |-<br /> | FlexIO || High-speed I/O interface || 2.5Ghz (RC_REFCLK : 500MHz 1:5 PLL) || Flex I/O to [[RSX]]<br /> |-<br /> | L2 || Level 2 cache || 3.2GHz (NCLK) || 512KB L2 cache for PPE<br /> |-<br /> | MIC || Memory interface controller || 1.6GHz (NCLK/2) || Memory controller to XIO(/Rambus XDR)<br /> |-<br /> | MBL || MIC bus logic || 1.6GHz (NCLK/2) || From MIC(/PPE) to EIB(/SPE's)<br /> |-<br /> | PPE || Power processor element || 3.2GHz (NCLK) || Main dualthreaded CPU<br /> |-<br /> | SPE || Synergistic processor element || &lt;span title=&quot;see SPU table below&quot;&gt;3.2GHz/1.6GHz&lt;/span&gt; || 8 present, 1 disabled from factory<br /> |-<br /> | XIO || Extreme data rate I/O cell || 1.6GHz (Y0_RQ_CTM/Y1_RQ_CTM : 400MHz 1:4 PLL) || Rambus XDR Interface<br /> |-<br /> | TEST || Test control unit (TCU) / pervasive logic (PRV) || || Used for power management, thermal management, clock control, software-performance monitoring, trace analysis, preboot (and secureboot?), &lt;br /&gt;also has RAS-unit (Reliability, Availability, Serviceability), JTAG (IEEE 1149 test access port) and SPI Serial Peripheral Interface<br /> |-<br /> | PLL || Phase-Locked Loop || 400MHz || Before preboot external clock (400MHz) is used (see [[Timebases]])&lt;br /&gt;afterwards only internal PLL (PLL_REFCLK : 400MHz 1:8 PLL) for main clocks: NCLK=3.2GHz, NCLK/2=1.6GHz, MiClk=1.6GHz, XIO Clk=1.6GHz, BClk=1.667GHz, RO/TO Clk=2.5GHz<br /> |-<br /> |}<br /> <br /> === SPE ===<br /> &lt;div style=&quot;float:right&quot;&gt;[[File:SPU-diagram-DMA.png|200px|thumb|left|CellBE - SPU diagram]]&lt;/div&gt;<br /> <br /> {| border=&quot;1&quot; cellspacing=&quot;0&quot; cellpadding=&quot;5&quot; border=&quot;#999&quot; class=&quot;wikitable&quot; style=&quot;border:1px solid #999; border-collapse: collapse;&quot; <br /> |- bgcolor=&quot;#cccccc&quot;<br /> ! ABBR !! Usage !! Speed !! Notes<br /> |-<br /> | BIU || Bus interface unit || 1.6GHz (NCLK/2) || connects DMAC+EIB and LS+EIB<br /> |-<br /> | DMAC || Direct memory access controller || 1.6GHz (NCLK/2) || controls DMA, SPU+LS and BIU(/EIB)<br /> |-<br /> | EIB || Element interconnect bus || 1.6GHz (NCLK/2) || busring to which all SPE's are connected (and PPU + MIC + BEI)<br /> |-<br /> | LS || Local store || 3.2GHz (NCLK) || 256KB of local memory, accessable via DMA/MBOX<br /> |-<br /> | MFC || Memory flow controller || 1.6GHz (NCLK/2) || <br /> |-<br /> | MIC || Memory interface controller || 1.6GHz (NCLK/2) || Memory controller to XIO(/Rambus XDR)<br /> |-<br /> | MMIO || Memory-mapped I/O || 1.6GHz (NCLK/2) || <br /> |-<br /> | MMU || Memory management unit || 1.6GHz (NCLK/2) || used by DMAC for management<br /> |-<br /> | SPU || Synergistic processor unit || 3.2GHz (NCLK) || SPU execution unit<br /> |-<br /> | TLB || Translation lookaside buffer || 1.6GHz (NCLK/2) || used by MMU as buffer<br /> |-<br /> |}<br /> <br /> Reference: http://hpc.pnl.gov/people/fabrizio/papers/ieeemicro-cell.pdf // backup/mirror: [http://www.multiupload.com/UN7VJHHER1 ieeemicro-cell.pdf (222.51 KB)]<br /> <br /> == Bandwith I/O ==<br /> &lt;div style=&quot;float:right&quot;&gt;[[File:Cellbe-bandwith.gif|200px|thumb|left|CellBE bandwidth]]&lt;/div&gt;<br /> <br /> * MIC (Memory Interface Controller) &amp;lt;from/to&amp;gt; [[RAM#Main_System_Memory|dual Rambus XDR]]: 25.6GB/s theoretical<br /> <br /> * IOIF0 (I/O Interface to RSX): 20GB/s to&amp;gt; [[RSX]] / 15 GB/s &amp;lt; [[RSX]] ([[RSX]] &amp;lt;from/to&amp;gt; [[RAM#Graphics_Memory|GDDR3]]: 20.8GB/s @ 650MHz)<br /> <br /> * IOIF1 (I/O Interface to Southbridge): &amp;lt;from/to&amp;gt; [[South Bridge]] : 2.5GB/s <br /> <br /> * EIB (Element Interconnect Bus) : 4x 128bit buses / 128byte packets : 204.8 GB/s total<br /> <br /> * PPU (PowerPC Processing Element) : 25.6 GLOP/s FPU, L1/L2: 51.2GB/s<br /> <br /> * LHS (Load Hit Store) pipeline stall : ~40 clockcycles<br /> <br /> * SPE (Synergistic Processor Elements) : 2 IPC SPU to Local Store : 51.2GB/s<br /> <br /> Reference: [http://www.ibm.com/developerworks/power/library/pa-cellperf/ Cell Broadband Engine Architecture and its first implementation - A performance view]<br /> <br /> <br /> == Serial Numbers @ SKU ==<br /> The Cell BE was introduced at 90nm. Later, PS3 model numbers starting with CECHG uses the 65nm version, while the PS3 Slim (CECH-20xx) used the 45nm version (See [[SKU Models]] and table below).<br /> <br /> A sampling of the serial numbers by model number.<br /> {| border=&quot;1&quot; cellspacing=&quot;0&quot; cellpadding=&quot;5&quot; border=&quot;#999&quot; class=&quot;wikitable&quot; style=&quot;border:1px solid #999; border-collapse: collapse;&quot; <br /> |- bgcolor=&quot;#cccccc&quot;<br /> ! PS3 Model !! Mobo Model !! Mobo serial !! CELL Serial !! Die Tech !! Total Die Size !! Width x Length !! SPU size !! PPE Size !! Remark<br /> |-<br /> | [[CECHAxx]] || [[COK-00x#COK-001|COK-001]] || - || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHAxx]] || [[COK-00x#COK-001|COK-001]] || 1-871-868-12 || [[CXD2964AGB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHAxx]] || [[COK-00x#COK-001|COK-001]] || 1-871-868-22 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHAxx]] || [[COK-00x#COK-001|COK-001]] || 1-871-868-32 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHBxx]] || [[COK-00x#COK-001|COK-001]] || - || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHBxx]] || [[COK-00x#COK-001|COK-001]] || 1-871-868-22 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHBxx]] || [[COK-00x#COK-001|COK-001]] || 1-871-868-32 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHCxx]] || [[COK-00x#COK-002|COK-002]] || 1-873-513-21&lt;br /&gt;1-873-513-31 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;[[CECHDxx]]&lt;/span&gt; || colspan=&quot;9&quot; style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;SKU never released&lt;/span&gt;<br /> |-<br /> | [[CECHExx]] || [[COK-00x#COK-002W|COK-002W]] || - || CXD29?? || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHExx]] || [[COK-00x#COK-002W|COK-002W]] || 1-873-513-21 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHExx]] || [[COK-00x#COK-002W|COK-002W]] || 1-873-513-21 || [[CXD2964AGB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHExx]] || [[COK-00x#COK-002W|COK-002W]] || 1-873-513-31 || [[CXD2964AGB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHExx]] || [[COK-00x#COK-002W|COK-002W]] || 1-873-513-31 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;[[CECHFxx]]&lt;/span&gt; || colspan=&quot;9&quot; style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;SKU never released&lt;/span&gt;<br /> |-<br /> | [[CECHGxx]] || [[SEM-00x|SEM-001]] || 1-875-384-11&lt;br /&gt;1-875-384-21&lt;br /&gt;1-875-384-31 || [[CXD2981AGB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHHxx]] || [[DIA-00x#DIA-001|DIA-001]] || 1-875-368-11&lt;br /&gt;1-875-368-31 || [[CXD2981GB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHHxx]] || [[DIA-00x#DIA-001|DIA-001]] || 1-875-938-11 || [[CXD2981AGB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHHxx]] || [[DIA-00x#DIA-001|DIA-001]] || 1-875-938-31 || [[CXD2981AGB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;[[CECHIxx]]&lt;/span&gt; || colspan=&quot;9&quot; style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;SKU never released&lt;/span&gt;<br /> |-<br /> | [[CECHJxx]] || [[DIA-00x#DIA-002|DIA-002]] || 1-876-912-31 || [[CXD2981GB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHKxx]] || [[DIA-00x#DIA-002|DIA-002]] || 1-876-912-32 || [[CXD2989AGB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHLxx]] || [[VER-00x|VER-001]] || - || [[CXD2990AGB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHLxx]] || [[VER-00x|VER-001]] || 1-878-196-31 || [[CXD2990GB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHMxx]] || [[VER-00x|VER-001]] || ?1-878-196-41? || -? || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || -?<br /> |-<br /> | style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;[[CECHNxx]]&lt;/span&gt; || colspan=&quot;9&quot; style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;SKU never released&lt;/span&gt;<br /> |-<br /> | style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;[[CECHOxx]]&lt;/span&gt; || colspan=&quot;9&quot; style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;SKU never released&lt;/span&gt;<br /> |-<br /> | [[CECHPxx]] || [[VER-00x|VER-001]] || ?1-878-196-41? || -? || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || -?<br /> |-<br /> | [[CECHQxx]] || [[VER-00x|VER-001]] || ?1-878-196-41? || CXD299? || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECH-20xx]] || [[DYN-00x|DYN-001]] || - || [[CXD2992AGB]] || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECH-20xx]] || [[DYN-00x|DYN-001]] || 1-880-055-31 || [[CXD2992AGB]] || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECH-21xx]] || [[SUR-00x|SUR-001]] || - || [[CXD2992AGB]] || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECH-21xx]] || [[SUR-00x|SUR-001]] || 1-881-945-11 || [[CXD2992AGB]] || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECH-25xx]] || [[JTP-00x|JTP-001]] || 1-882-481-31 || [[CXD2992GB]] || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECH-25xx]] || [[JSD-00x|JSD-001]] || 1-882-481-31 || [[CXD2992GB]]? || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || <br /> |-<br /> | [[CECH-30xx]] || [[KTE-00x|KTE-001]] || 1-884-749-11 || [[CXD2996GB]]? || 45nm? || 115.46mm²? || 12.75mm x 9.06mm? || 6.47mm²? || 11.32mm²? || -?<br /> |-<br /> | [[CECH-40xx]] || [[MSX-00x|MSX-001]] || 1-886-928-11 || [[CXD2996BGB]] || 45nm? || 115.46mm²? || 12.75mm x 9.06mm? || 6.47mm²? || 11.32mm²? || -?<br /> |-<br /> | [[CECH-40xx]] || [[MPX-00x|MPX-001]] || 1-887-233-11 || [[CXD2996BGB]] || 45nm? || 115.46mm²? || 12.75mm x 9.06mm? || 6.47mm²? || 11.32mm²? || -?<br /> |-<br /> | [[CECH-42xx]] || [[PQX-00x|PQX-001]] || 1-888-629-22 || [[CXD2996BGB]] || ?nm || ?mm² || ?mm x ?mm || 6.47mm²? || ?mm² || [http://www.mobile01.com/topicdetail.php?f=281&amp;t=3747667&amp;p=1#mobile01.tw PS3/PS4]<br /> |-<br /> |}<br /> ===Alternative listing===<br /> * [[CECHAxx]]/[[COK-00x#COK-001|COK-001]], [[CECHBxx]]/[[COK-00x#COK-001|COK-001]] and [[CECHCxx]]/[[COK-00x#COK-002|COK-002]] : [[CXD2964AGB]] (CELL 90nm)<br /> * [[CECHAxx]]/[[COK-00x#COK-001|COK-001]] : [[CXD2964GB]] (CELL 90nm)<br /> * [[CECHGxx]]/[[SEM-00x|SEM-001]] and [[CECHHxx]]/[[DIA-00x#DIA-001|DIA-001]] : [[CXD2981AGB]] (CELL 65nm)<br /> * [[CECHJxx]]/[[DIA-00x#DIA-002|DIA-002]] and [[CECHKxx]]/[[DIA-00x#DIA-002|DIA-002]] : [[CXD2989]] (CELL 65nm)<br /> * [[CECHLxx]]/[[VER-00x|VER-001]] up and including [[CECHQxx]]/[[VER-00x|VER-001]] : [[CXD2990ABG]] (CELL 65nm)<br /> * [[CECH-20xx]]/[[DYN-00x|DYN-001]], [[CECH-21xx]]/[[SUR-00x|SUR-001]], [[CECH-25xx]]/[[JTP-00x|JTP-001]] and [[CECH-25xx]]/[[JTP-00x|JTP-001]] : [[CXD2992AGB]] (CELL 45nm)<br /> * [[CECH-30xx]]/[[KTE-00x|KTE-001]] : [[CXD2996GB]] (CELL 45nm)<br /> * [[CECH-40xx]]/[[MSX-00x|MSX-001]] : [[CXD2996GB]] (CELL 45nm)<br /> * [[CECH-42xx]]/[[PQX-00x|PQX-001]] : [[CXD2999AGG]] (CELL ?nm)<br /> &lt;br /&gt;<br /> <br /> == PVR (powerpc version register) ==<br /> The PVR inside the microprocessor is the only way to identify what version of what part you have.<br /> <br /> cat /proc/cpuinfo<br /> <br /> or<br /> <br /> unsigned int pvr;<br /> __asm__ __volatile__ (&quot;mfpvr %0&quot; : &quot;=r&quot; (pvr));<br /> <br /> code above should work in kernel &amp; user mode. &lt;!-- http://lists.freebsd.org/pipermail/svn-src-head/2010-February/014780.html --&gt;<br /> <br /> {| border=&quot;1&quot; cellspacing=&quot;0&quot; cellpadding=&quot;5&quot; border=&quot;#999&quot; class=&quot;wikitable sortable&quot; style=&quot;border:1px solid #999; border-collapse: collapse;&quot; <br /> |- bgcolor=&quot;#cccccc&quot;<br /> ! CellBE serial !! die tech !! PVR !! Notes<br /> |-<br /> | [[CXD2964AGB]] || 90nm || || <br /> |-<br /> | [[CXD2964GB]] || 90nm || || <br /> |-<br /> | [[CXD2981AGB]] || 65nm || || <br /> |-<br /> | [[CXD2981GB]] || 65nm || || <br /> |-<br /> | [[CXD2989AGB]] || 65nm || || <br /> |-<br /> | [[CXD2989GB]] || 65nm || || <br /> |-<br /> | [[CXD2990AGB]] || 65nm || || <br /> |-<br /> | [[CXD2990GB]] || 65nm || || <br /> |-<br /> | [[CXD2992AGB]] || 45nm || || <br /> |-<br /> | [[CXD2992GB]] || 45nm || || <br /> |-<br /> | [[CXD2996GB]] || 45nm || || <br /> |-<br /> | [[CXD2999AGG]] || || || <br /> |-<br /> |}<br /> <br /> === Cell Revisions ===<br /> <br /> {| border=&quot;1&quot; cellspacing=&quot;0&quot; cellpadding=&quot;5&quot; border=&quot;#999&quot; class=&quot;wikitable sortable&quot; style=&quot;border:1px solid #999; border-collapse: collapse;&quot; <br /> |- bgcolor=&quot;#cccccc&quot;<br /> ! CellBE Version !! PVR !! Speed<br /> |-<br /> | Cell/BE v1.0 || 0x0070 0x0100 || 2.4GHz<br /> |-<br /> | Cell/BE v2.0 || 0x0070 0x0400 || 2.4GHz<br /> |-<br /> | Cell/BE v3.0 || 0x0070 0x0500 || 3.2GHz<br /> |-<br /> | Cell/BE v3.1 || 0x0070 0x0501 || 3.2GHz<br /> |-<br /> | Cell/BE v3.2 || 0x0070 0x0501 || 3.2GHz<br /> |-<br /> | ???? || 0x0070 0x2100 || <br /> |-<br /> |}<br /> <br /> == Unsorted ==<br /> === Integrated Heat Spreader (IHS) removed pic's ===<br /> <br /> * when it goes OK: http://imageshack.us/f/855/imgp0048v.jpg/ http://imageshack.us/f/850/imgp0046i.jpg/<br /> <br /> * when it goes wrong: http://postimage.org/image/hl11y3969/full/ http://postimage.org/image/bbydh5s6v/full/<br /> <br /> === IHS size and mounting ===<br /> on a COK-001 the CPU heatspreader is 4.00cm x 4.00cm while the RSX heatspreader is 4.25cm x 4.25 cm - CPU and RSX mountholes are 8.75cm apart and 6.3mm diameter<br /> <br /> although a PC cooler should fit within these dimensions fine, mounting the 2 (which are also elevated differently from the motherboard) can be problematic<br /> <br /> <br /> <br /> {{Motherboard Components}}&lt;noinclude&gt;[[Category:Main]]&lt;/noinclude&gt;</div> 114.34.113.113 http://www.psdevwiki.com/ps3/index.php?title=CELL_BE&diff=26873 CELL BE 2014-02-12T19:53:50Z <p>114.34.113.113: Add new CELL BE serial</p> <hr /> <div>= Cell Broadband Engine =<br /> <br /> &lt;div style=&quot;float:right&quot;&gt;[[File:CellBE.jpg|200px|thumb|left|Cell Broadband Engine&lt;br /&gt;CPU with heatplate&lt;br /&gt;CXD2992AGB]]&lt;br /&gt;[[File:CXD2992AGB 46J2494 diemrk1.jpg|200px|thumb|left|IBM markings in CXD2992AGB die]]&lt;/div&gt;<br /> <br /> The Cell CPU has one 3.2Ghz PPE (Power Processor Element) with two threads and eight 3.2Ghz SPE (Synergistic Processing Elements).<br /> <br /> The PPE is a general purpose CPU, while the eight SPE are geared towards processing data in parallel. One SPE is disabled to increase yield, so the PS3 can have at most 9 threads runnings at the same time (2 from PPE and 7 from SPE). Note that one SPE is reserved for the hypervisor, so PS3 programs can take advantage of 8 threads. Both the PPE and SPE of the Cell are 64 bit, and manipulate data in Big Endian.<br /> <br /> == Specifications ==<br /> <br /> * 1 PPE (Power Processor Element)<br /> ** 3.2Ghz<br /> ** 64 bit, Big Endian<br /> ** 2 threads (can run at same time)<br /> ** L1 cache: 32kB data + 32kB instruction<br /> ** L2 cache: 512kB<br /> ** Memory bus width: 64bit (serial)<br /> ** VMX (Altivec) instruction set support<br /> ** Full IEEE-754 compliant <br /> ** the PPU can execute two double precision or eight single precision operations per clockcycle<br /> * 8 SPE (Synergistic Processing Element)<br /> ** 3.2Ghz<br /> ** 64 bit, Big Endian<br /> ** 1 SPE disabled to improve chip yield (see: [[Unlocking the 8th SPE]])<br /> ** 1 SPE dedicated for hypervisor security<br /> ** 256KB local store per SPE<br /> ** 128 registers per SPE<br /> ** Dual Issue (Each SPE can execute 2 instructions per clock)<br /> ** IEEE-754 compliant in double precision (single precision round-towards-zero instead of round-towards-even)<br /> <br /> There is a lot of info about CELL/BE on the [[Cell Programming IBM]] page.<br /> <br /> == Die explained ==<br /> &lt;table width=&quot;100%&quot; align=&quot;left&quot;&gt;&lt;tr&gt;<br /> &lt;td align=&quot;left&quot;&gt;[[File:CELLBE die large.jpg|200px|thumb|left|Cell Broadband Engine&lt;br /&gt;Die - 90nm]]&lt;/td&gt;<br /> &lt;td align=&quot;left&quot;&gt;[[File:SPU-DIE.PNG|140px|thumb|left|Cell Broadband Engine&lt;br /&gt;SPU Die map]]&lt;/td&gt;<br /> &lt;td align=&quot;left&quot;&gt;[[File:CellBE-map-90nm.jpg|200px|thumb|left|Cell Broadband Engine&lt;br /&gt;Die map - 90nm]]&lt;/td&gt;<br /> &lt;td align=&quot;left&quot;&gt;[[File:CellBE-map-65nm.jpg|200px|thumb|left|Cell Broadband Engine&lt;br /&gt;Die map - 65nm]]&lt;/td&gt;<br /> &lt;td align=&quot;left&quot;&gt;[[File:CellBE-map-45nm.jpg|200px|thumb|left|Cell Broadband Engine&lt;br /&gt;Die map - 45nm]]&lt;/td&gt;<br /> &lt;/tr&gt;&lt;/table&gt;<br /> <br /> &lt;div style=&quot;float:right&quot;&gt;[[File:Cell-90nm-die.png|200px|thumb|left|CellBE 90nm die]]&lt;/div&gt;<br /> {| border=&quot;1&quot; cellspacing=&quot;0&quot; cellpadding=&quot;5&quot; border=&quot;#999&quot; class=&quot;wikitable&quot; style=&quot;border:1px solid #999; border-collapse: collapse;&quot; <br /> |- bgcolor=&quot;#cccccc&quot;<br /> ! ABBR !! Usage !! Speed !! Notes<br /> |-<br /> | BEI || Broadband engine interface || 1.6GHz (NCLK/2) || I/O Controller to FlexIO(/RSX)<br /> |-<br /> | EIB || Element interconnect bus || 1.6GHz (NCLK/2) || used as communication ring for the 8 SPE (and PPU + MIC + BEI)<br /> |-<br /> | FlexIO || High-speed I/O interface || 2.5Ghz (RC_REFCLK : 500MHz 1:5 PLL) || Flex I/O to [[RSX]]<br /> |-<br /> | L2 || Level 2 cache || 3.2GHz (NCLK) || 512KB L2 cache for PPE<br /> |-<br /> | MIC || Memory interface controller || 1.6GHz (NCLK/2) || Memory controller to XIO(/Rambus XDR)<br /> |-<br /> | MBL || MIC bus logic || 1.6GHz (NCLK/2) || From MIC(/PPE) to EIB(/SPE's)<br /> |-<br /> | PPE || Power processor element || 3.2GHz (NCLK) || Main dualthreaded CPU<br /> |-<br /> | SPE || Synergistic processor element || &lt;span title=&quot;see SPU table below&quot;&gt;3.2GHz/1.6GHz&lt;/span&gt; || 8 present, 1 disabled from factory<br /> |-<br /> | XIO || Extreme data rate I/O cell || 1.6GHz (Y0_RQ_CTM/Y1_RQ_CTM : 400MHz 1:4 PLL) || Rambus XDR Interface<br /> |-<br /> | TEST || Test control unit (TCU) / pervasive logic (PRV) || || Used for power management, thermal management, clock control, software-performance monitoring, trace analysis, preboot (and secureboot?), &lt;br /&gt;also has RAS-unit (Reliability, Availability, Serviceability), JTAG (IEEE 1149 test access port) and SPI Serial Peripheral Interface<br /> |-<br /> | PLL || Phase-Locked Loop || 400MHz || Before preboot external clock (400MHz) is used (see [[Timebases]])&lt;br /&gt;afterwards only internal PLL (PLL_REFCLK : 400MHz 1:8 PLL) for main clocks: NCLK=3.2GHz, NCLK/2=1.6GHz, MiClk=1.6GHz, XIO Clk=1.6GHz, BClk=1.667GHz, RO/TO Clk=2.5GHz<br /> |-<br /> |}<br /> <br /> === SPE ===<br /> &lt;div style=&quot;float:right&quot;&gt;[[File:SPU-diagram-DMA.png|200px|thumb|left|CellBE - SPU diagram]]&lt;/div&gt;<br /> <br /> {| border=&quot;1&quot; cellspacing=&quot;0&quot; cellpadding=&quot;5&quot; border=&quot;#999&quot; class=&quot;wikitable&quot; style=&quot;border:1px solid #999; border-collapse: collapse;&quot; <br /> |- bgcolor=&quot;#cccccc&quot;<br /> ! ABBR !! Usage !! Speed !! Notes<br /> |-<br /> | BIU || Bus interface unit || 1.6GHz (NCLK/2) || connects DMAC+EIB and LS+EIB<br /> |-<br /> | DMAC || Direct memory access controller || 1.6GHz (NCLK/2) || controls DMA, SPU+LS and BIU(/EIB)<br /> |-<br /> | EIB || Element interconnect bus || 1.6GHz (NCLK/2) || busring to which all SPE's are connected (and PPU + MIC + BEI)<br /> |-<br /> | LS || Local store || 3.2GHz (NCLK) || 256KB of local memory, accessable via DMA/MBOX<br /> |-<br /> | MFC || Memory flow controller || 1.6GHz (NCLK/2) || <br /> |-<br /> | MIC || Memory interface controller || 1.6GHz (NCLK/2) || Memory controller to XIO(/Rambus XDR)<br /> |-<br /> | MMIO || Memory-mapped I/O || 1.6GHz (NCLK/2) || <br /> |-<br /> | MMU || Memory management unit || 1.6GHz (NCLK/2) || used by DMAC for management<br /> |-<br /> | SPU || Synergistic processor unit || 3.2GHz (NCLK) || SPU execution unit<br /> |-<br /> | TLB || Translation lookaside buffer || 1.6GHz (NCLK/2) || used by MMU as buffer<br /> |-<br /> |}<br /> <br /> Reference: http://hpc.pnl.gov/people/fabrizio/papers/ieeemicro-cell.pdf // backup/mirror: [http://www.multiupload.com/UN7VJHHER1 ieeemicro-cell.pdf (222.51 KB)]<br /> <br /> == Bandwith I/O ==<br /> &lt;div style=&quot;float:right&quot;&gt;[[File:Cellbe-bandwith.gif|200px|thumb|left|CellBE bandwidth]]&lt;/div&gt;<br /> <br /> * MIC (Memory Interface Controller) &amp;lt;from/to&amp;gt; [[RAM#Main_System_Memory|dual Rambus XDR]]: 25.6GB/s theoretical<br /> <br /> * IOIF0 (I/O Interface to RSX): 20GB/s to&amp;gt; [[RSX]] / 15 GB/s &amp;lt; [[RSX]] ([[RSX]] &amp;lt;from/to&amp;gt; [[RAM#Graphics_Memory|GDDR3]]: 20.8GB/s @ 650MHz)<br /> <br /> * IOIF1 (I/O Interface to Southbridge): &amp;lt;from/to&amp;gt; [[South Bridge]] : 2.5GB/s <br /> <br /> * EIB (Element Interconnect Bus) : 4x 128bit buses / 128byte packets : 204.8 GB/s total<br /> <br /> * PPU (PowerPC Processing Element) : 25.6 GLOP/s FPU, L1/L2: 51.2GB/s<br /> <br /> * LHS (Load Hit Store) pipeline stall : ~40 clockcycles<br /> <br /> * SPE (Synergistic Processor Elements) : 2 IPC SPU to Local Store : 51.2GB/s<br /> <br /> Reference: [http://www.ibm.com/developerworks/power/library/pa-cellperf/ Cell Broadband Engine Architecture and its first implementation - A performance view]<br /> <br /> <br /> == Serial Numbers @ SKU ==<br /> The Cell BE was introduced at 90nm. Later, PS3 model numbers starting with CECHG uses the 65nm version, while the PS3 Slim (CECH-20xx) used the 45nm version (See [[SKU Models]] and table below).<br /> <br /> A sampling of the serial numbers by model number.<br /> {| border=&quot;1&quot; cellspacing=&quot;0&quot; cellpadding=&quot;5&quot; border=&quot;#999&quot; class=&quot;wikitable&quot; style=&quot;border:1px solid #999; border-collapse: collapse;&quot; <br /> |- bgcolor=&quot;#cccccc&quot;<br /> ! PS3 Model !! Mobo Model !! Mobo serial !! CELL Serial !! Die Tech !! Total Die Size !! Width x Length !! SPU size !! PPE Size !! Remark<br /> |-<br /> | [[CECHAxx]] || [[COK-00x#COK-001|COK-001]] || - || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHAxx]] || [[COK-00x#COK-001|COK-001]] || 1-871-868-12 || [[CXD2964AGB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHAxx]] || [[COK-00x#COK-001|COK-001]] || 1-871-868-22 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHAxx]] || [[COK-00x#COK-001|COK-001]] || 1-871-868-32 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHBxx]] || [[COK-00x#COK-001|COK-001]] || - || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHBxx]] || [[COK-00x#COK-001|COK-001]] || 1-871-868-22 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHBxx]] || [[COK-00x#COK-001|COK-001]] || 1-871-868-32 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHCxx]] || [[COK-00x#COK-002|COK-002]] || 1-873-513-21&lt;br /&gt;1-873-513-31 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;[[CECHDxx]]&lt;/span&gt; || colspan=&quot;9&quot; style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;SKU never released&lt;/span&gt;<br /> |-<br /> | [[CECHExx]] || [[COK-00x#COK-002W|COK-002W]] || - || CXD29?? || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHExx]] || [[COK-00x#COK-002W|COK-002W]] || 1-873-513-21 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHExx]] || [[COK-00x#COK-002W|COK-002W]] || 1-873-513-21 || [[CXD2964AGB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHExx]] || [[COK-00x#COK-002W|COK-002W]] || 1-873-513-31 || [[CXD2964AGB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHExx]] || [[COK-00x#COK-002W|COK-002W]] || 1-873-513-31 || [[CXD2964GB]] || 90nm || 235.48mm² || 19.17mm x 12.29mm || 14.76mm² || 28.86mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;[[CECHFxx]]&lt;/span&gt; || colspan=&quot;9&quot; style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;SKU never released&lt;/span&gt;<br /> |-<br /> | [[CECHGxx]] || [[SEM-00x|SEM-001]] || 1-875-384-11&lt;br /&gt;1-875-384-21&lt;br /&gt;1-875-384-31 || [[CXD2981AGB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHHxx]] || [[DIA-00x#DIA-001|DIA-001]] || 1-875-368-11&lt;br /&gt;1-875-368-31 || [[CXD2981GB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHHxx]] || [[DIA-00x#DIA-001|DIA-001]] || 1-875-938-11 || [[CXD2981AGB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHHxx]] || [[DIA-00x#DIA-001|DIA-001]] || 1-875-938-31 || [[CXD2981AGB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;[[CECHIxx]]&lt;/span&gt; || colspan=&quot;9&quot; style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;SKU never released&lt;/span&gt;<br /> |-<br /> | [[CECHJxx]] || [[DIA-00x#DIA-002|DIA-002]] || 1-876-912-31 || [[CXD2981GB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHKxx]] || [[DIA-00x#DIA-002|DIA-002]] || 1-876-912-32 || [[CXD2989AGB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHLxx]] || [[VER-00x|VER-001]] || - || [[CXD2990AGB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECHLxx]] || [[VER-00x|VER-001]] || 1-878-196-31 || [[CXD2990GB]] || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECHMxx]] || [[VER-00x|VER-001]] || ?1-878-196-41? || -? || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || -?<br /> |-<br /> | style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;[[CECHNxx]]&lt;/span&gt; || colspan=&quot;9&quot; style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;SKU never released&lt;/span&gt;<br /> |-<br /> | style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;[[CECHOxx]]&lt;/span&gt; || colspan=&quot;9&quot; style=&quot;text-align:center; background-color:lightgrey;&quot; | &lt;span style=&quot;background-color:lightgrey;&quot;&gt;SKU never released&lt;/span&gt;<br /> |-<br /> | [[CECHPxx]] || [[VER-00x|VER-001]] || ?1-878-196-41? || -? || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || -?<br /> |-<br /> | [[CECHQxx]] || [[VER-00x|VER-001]] || ?1-878-196-41? || CXD299? || 65nm || 174.61mm² || 15.59mm x 11.20mm || 11.08mm² || 19.60mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECH-20xx]] || [[DYN-00x|DYN-001]] || - || [[CXD2992AGB]] || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECH-20xx]] || [[DYN-00x|DYN-001]] || 1-880-055-31 || [[CXD2992AGB]] || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECH-21xx]] || [[SUR-00x|SUR-001]] || - || [[CXD2992AGB]] || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECH-21xx]] || [[SUR-00x|SUR-001]] || 1-881-945-11 || [[CXD2992AGB]] || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || [http://reballing.es/viewtopic.php?f=13&amp;t=2131 reballing.es]<br /> |-<br /> | [[CECH-25xx]] || [[JTP-00x|JTP-001]] || 1-882-481-31 || [[CXD2992GB]] || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || [http://www.edepot.com/playstation3.html#PS3_RSX_GPU edepot ps3secrets]<br /> |-<br /> | [[CECH-25xx]] || [[JSD-00x|JSD-001]] || 1-882-481-31 || [[CXD2992GB]]? || 45nm || 115.46mm² || 12.75mm x 9.06mm || 6.47mm² || 11.32mm² || <br /> |-<br /> | [[CECH-30xx]] || [[KTE-00x|KTE-001]] || 1-884-749-11 || [[CXD2996GB]]? || 45nm? || 115.46mm²? || 12.75mm x 9.06mm? || 6.47mm²? || 11.32mm²? || -?<br /> |-<br /> | [[CECH-40xx]] || [[MSX-00x|MSX-001]] || 1-886-928-11 || [[CXD2996BGB]] || 45nm? || 115.46mm²? || 12.75mm x 9.06mm? || 6.47mm²? || 11.32mm²? || -?<br /> |-<br /> | [[CECH-40xx]] || [[MPX-00x|MPX-001]] || 1-887-233-11 || [[CXD2996BGB]] || 45nm? || 115.46mm²? || 12.75mm x 9.06mm? || 6.47mm²? || 11.32mm²? || -?<br /> |-<br /> |}<br /> ===Alternative listing===<br /> * [[CECHAxx]]/[[COK-00x#COK-001|COK-001]], [[CECHBxx]]/[[COK-00x#COK-001|COK-001]] and [[CECHCxx]]/[[COK-00x#COK-002|COK-002]] : [[CXD2964AGB]] (CELL 90nm)<br /> * [[CECHAxx]]/[[COK-00x#COK-001|COK-001]] : [[CXD2964GB]] (CELL 90nm)<br /> * [[CECHGxx]]/[[SEM-00x|SEM-001]] and [[CECHHxx]]/[[DIA-00x#DIA-001|DIA-001]] : [[CXD2981AGB]] (CELL 65nm)<br /> * [[CECHJxx]]/[[DIA-00x#DIA-002|DIA-002]] and [[CECHKxx]]/[[DIA-00x#DIA-002|DIA-002]] : [[CXD2989]] (CELL 65nm)<br /> * [[CECHLxx]]/[[VER-00x|VER-001]] up and including [[CECHQxx]]/[[VER-00x|VER-001]] : [[CXD2990ABG]] (CELL 65nm)<br /> * [[CECH-20xx]]/[[DYN-00x|DYN-001]], [[CECH-21xx]]/[[SUR-00x|SUR-001]], [[CECH-25xx]]/[[JTP-00x|JTP-001]] and [[CECH-25xx]]/[[JTP-00x|JTP-001]] : [[CXD2992AGB]] (CELL 45nm)<br /> * [[CECH-30xx]]/[[KTE-00x|KTE-001]] : [[CXD2996GB]] (CELL 45nm)<br /> * [[CECH-40xx]]/[[MSX-00x|MSX-001]] : [[CXD2996GB]] (CELL 45nm)<br /> &lt;br /&gt;<br /> <br /> == PVR (powerpc version register) ==<br /> The PVR inside the microprocessor is the only way to identify what version of what part you have.<br /> <br /> cat /proc/cpuinfo<br /> <br /> or<br /> <br /> unsigned int pvr;<br /> __asm__ __volatile__ (&quot;mfpvr %0&quot; : &quot;=r&quot; (pvr));<br /> <br /> code above should work in kernel &amp; user mode. &lt;!-- http://lists.freebsd.org/pipermail/svn-src-head/2010-February/014780.html --&gt;<br /> <br /> {| border=&quot;1&quot; cellspacing=&quot;0&quot; cellpadding=&quot;5&quot; border=&quot;#999&quot; class=&quot;wikitable sortable&quot; style=&quot;border:1px solid #999; border-collapse: collapse;&quot; <br /> |- bgcolor=&quot;#cccccc&quot;<br /> ! CellBE serial !! die tech !! PVR !! Notes<br /> |-<br /> | [[CXD2964AGB]] || 90nm || || <br /> |-<br /> | [[CXD2964GB]] || 90nm || || <br /> |-<br /> | [[CXD2981AGB]] || 65nm || || <br /> |-<br /> | [[CXD2981GB]] || 65nm || || <br /> |-<br /> | [[CXD2989AGB]] || 65nm || || <br /> |-<br /> | [[CXD2989GB]] || 65nm || || <br /> |-<br /> | [[CXD2990AGB]] || 65nm || || <br /> |-<br /> | [[CXD2990GB]] || 65nm || || <br /> |-<br /> | [[CXD2992AGB]] || 45nm || || <br /> |-<br /> | [[CXD2992GB]] || 45nm || || <br /> |-<br /> | [[CXD2996GB]] || 45nm || || <br /> |-<br /> | [[CXD2999AGG]] || || || <br /> |-<br /> |}<br /> <br /> === Cell Revisions ===<br /> <br /> {| border=&quot;1&quot; cellspacing=&quot;0&quot; cellpadding=&quot;5&quot; border=&quot;#999&quot; class=&quot;wikitable sortable&quot; style=&quot;border:1px solid #999; border-collapse: collapse;&quot; <br /> |- bgcolor=&quot;#cccccc&quot;<br /> ! CellBE Version !! PVR !! Speed<br /> |-<br /> | Cell/BE v1.0 || 0x0070 0x0100 || 2.4GHz<br /> |-<br /> | Cell/BE v2.0 || 0x0070 0x0400 || 2.4GHz<br /> |-<br /> | Cell/BE v3.0 || 0x0070 0x0500 || 3.2GHz<br /> |-<br /> | Cell/BE v3.1 || 0x0070 0x0501 || 3.2GHz<br /> |-<br /> | Cell/BE v3.2 || 0x0070 0x0501 || 3.2GHz<br /> |-<br /> | ???? || 0x0070 0x2100 || <br /> |-<br /> |}<br /> <br /> == Unsorted ==<br /> === Integrated Heat Spreader (IHS) removed pic's ===<br /> <br /> * when it goes OK: http://imageshack.us/f/855/imgp0048v.jpg/ http://imageshack.us/f/850/imgp0046i.jpg/<br /> <br /> * when it goes wrong: http://postimage.org/image/hl11y3969/full/ http://postimage.org/image/bbydh5s6v/full/<br /> <br /> === IHS size and mounting ===<br /> on a COK-001 the CPU heatspreader is 4.00cm x 4.00cm while the RSX heatspreader is 4.25cm x 4.25 cm - CPU and RSX mountholes are 8.75cm apart and 6.3mm diameter<br /> <br /> although a PC cooler should fit within these dimensions fine, mounting the 2 (which are also elevated differently from the motherboard) can be problematic<br /> <br /> <br /> <br /> {{Motherboard Components}}&lt;noinclude&gt;[[Category:Main]]&lt;/noinclude&gt;</div> 114.34.113.113