IOP/Deckard
MIPS
I/O processor - MIPS R3000A (PS1 main processor) used in PS2 since SCPH-10000 to SCPH-700XX. Runs at a 36.864 mHz clock speed. It is connected to an external 2 MB EDO-RAM chip. Later got replaced by a new IOP based around a PowerPC 405 core, but with an additional MIPS core.
Revisions
- 1.5 : CXD9553GB (GH-001, GH-003)
- 1.15: CXD9619GB (GH-004 - GH-014, GH-016)
- 2.0 : CXD9660GB (earlier GH-015)
- 2.1 : CXD9697GP (later GH-015, erroneously listed as "CXD9697GB" in service manuals?)
- 2.1 : CXD9732GP (GH-017 - GH-022)
- 2.2 : CXD9783GP (GH-023)
- 2.4 : CXD9798GP (some GH-026 boards, maybe J-chassis GH-029?)
- 2.4 : CXD9799GP (PSX XPD-001/XPD-005, Namco System 256, some K-chassis slim boards, some GH-026 boards, maybe J-chassis GH-029?)
- 2.4 : CXD9799AGP (some K-chassis slim boards, Namco System 147, Namco System 148)
PowerPC
PowerPC 405 chip that replaced IOP and SPEED. It is connected to an external 4 MB DDR-SDRAM chip. In IOP emulator mode 2MB are used as a IOP memory. In PS2 used since SCPH-750XX model. New chip require some compatibility tweaks that are done per title by xparam file found in PS2 BOOTROM.
Note: There is some evidence that the new IOP additionally contain some kind of MIPS core connected thru AUX port.
Revisions
- 3.0 : CXD9796GP (SCPH-750XX series/L-chassis)
- As the only IOP revision to do so, this revision needs heatsinking!
- 3.0 : CXD9209GP (SCPH-770XX series/M-chassis)
Starting with N-chassis/SCPH-790XX, the IOP was integrated into the new main SoC together with its RAM. It still reports as version 3.0 in software.