Clocks: Difference between revisions
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Clock generation is based around one or two "DRCG-lite" (DRCG = Direct Rambus Clock Generator) clockgen ICs by varying manufacturers (Cypress CY2212 or TI CDCR61A). | Clock generation is based around one or two "DRCG-lite" (DRCG = Direct Rambus Clock Generator) clockgen ICs by varying manufacturers (Cypress CY2212 or TI CDCR61A). | ||
All of these boards have an DRCG-lite IC which has an 18.432 Mhz XTAL connected to it's inputs. This DRCG-lite is set for a multiplier of 64/3 and thus creates a 393.216 Mhz clock. | ===DRCG-lite #1=== | ||
All of these boards have an DRCG-lite IC which has an 18.432 Mhz XTAL connected to it's inputs. This DRCG-lite is set for a multiplier of 64/3 and thus creates a 393.216 Mhz clock for [[Emotion Engine|EE]] and [[Rambus DRAM|RDRAM]]. | |||
===DRCG-lite #2=== | |||
''This additional DRCG is not found on boards from the same chassis types that use the second revision GS (CXD2944GB) (GH-004, GH-006, GH-008, GH-010, GH-013).'' | |||
All boards that have the original [[Graphics_Synthesizer|GS]] with metal heat spreader, CXD2934GB (GH-001, GH-003, GH-005, GH-007, GH-012, GH-014, GH-016), have a second DRCG-lite IC (also with an 18.432 Mhz XTAL) which is set to a multiplier of 16 to generate a 294.912 Mhz clock which is fed into GS. | |||
= F, G, H chassis = | = F, G, H chassis = | ||
Based around one "DRCG-lite" and one "GMCG" (=Graphics Media Clock Generator) clock generator. The GMCG has a 18.432 Mhz XTAL and generates | Based around one "DRCG-lite" and one "GMCG" (=Graphics Media Clock Generator, e.g. Cypress CY24141) clock generator. | ||
===GMCG=== | |||
The GMCG has a 18.432 Mhz XTAL and generates a 54 Mhz or 53.9 Mhz clock for GS (selection between 54 and 53.9 is done via control line from [[DEV9C]], later from the SPU2+DEV9C-Controller combo IC) and also creates a 18.432 Mhz input clock for the DRCG-lite. | |||
===DRCG-lite=== | |||
The main clock output of DRCG-lite is set for a multiplier of 64/3 and thus creates a 393.216 Mhz clock for [[Emotion Engine|EE]] and [[Rambus DRAM|RDRAM]]. Additionally, DRCG lite generates a 9.216 Mhz clock signal for GS from the 18.432 Mhz input via a multiplier of 0.5. | |||
= I, J, K, L, M chassis = | = I, J, K, L, M chassis = | ||
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= N, P, R chassis = | = N, P, R chassis = | ||
Based around one single clock generator IC with an 18.432 Mhz XTAL. Part number on IC case is always (?) '''627G04LF'''. Not much else is known, since no public datasheet is available. | Based around one single clock generator IC with an 18.432 Mhz XTAL, similar, but not identical to the "GMCG" mentioned above. It outputs a 18.432 Mhz clock (for EE/the SoC of these chassis), a 25 Mhz clock (for the ethernet transceiver) and a (likely switchable) 54/53.9 Mhz clock (for GS, see above). Part number on IC case is always (?) '''627G04LF'''. Not much else is known, since no public datasheet is available. | ||
Latest revision as of 03:45, 24 November 2024
Overview[edit | edit source]
A, A+, AB, B, B', C, C', D, D' chassis[edit | edit source]
Clock generation is based around one or two "DRCG-lite" (DRCG = Direct Rambus Clock Generator) clockgen ICs by varying manufacturers (Cypress CY2212 or TI CDCR61A).
DRCG-lite #1[edit | edit source]
All of these boards have an DRCG-lite IC which has an 18.432 Mhz XTAL connected to it's inputs. This DRCG-lite is set for a multiplier of 64/3 and thus creates a 393.216 Mhz clock for EE and RDRAM.
DRCG-lite #2[edit | edit source]
This additional DRCG is not found on boards from the same chassis types that use the second revision GS (CXD2944GB) (GH-004, GH-006, GH-008, GH-010, GH-013).
All boards that have the original GS with metal heat spreader, CXD2934GB (GH-001, GH-003, GH-005, GH-007, GH-012, GH-014, GH-016), have a second DRCG-lite IC (also with an 18.432 Mhz XTAL) which is set to a multiplier of 16 to generate a 294.912 Mhz clock which is fed into GS.
F, G, H chassis[edit | edit source]
Based around one "DRCG-lite" and one "GMCG" (=Graphics Media Clock Generator, e.g. Cypress CY24141) clock generator.
GMCG[edit | edit source]
The GMCG has a 18.432 Mhz XTAL and generates a 54 Mhz or 53.9 Mhz clock for GS (selection between 54 and 53.9 is done via control line from DEV9C, later from the SPU2+DEV9C-Controller combo IC) and also creates a 18.432 Mhz input clock for the DRCG-lite.
DRCG-lite[edit | edit source]
The main clock output of DRCG-lite is set for a multiplier of 64/3 and thus creates a 393.216 Mhz clock for EE and RDRAM. Additionally, DRCG lite generates a 9.216 Mhz clock signal for GS from the 18.432 Mhz input via a multiplier of 0.5.
I, J, K, L, M chassis[edit | edit source]
Based around one single DRCG-lite compatible clock generator with an 18.432 Mhz XTAL, generating a 393.216 Mhz clock, which additionally also generates the selectable 54 Mhz or 53.9 Mhz clock (e.g. Cypress CY22313).
N, P, R chassis[edit | edit source]
Based around one single clock generator IC with an 18.432 Mhz XTAL, similar, but not identical to the "GMCG" mentioned above. It outputs a 18.432 Mhz clock (for EE/the SoC of these chassis), a 25 Mhz clock (for the ethernet transceiver) and a (likely switchable) 54/53.9 Mhz clock (for GS, see above). Part number on IC case is always (?) 627G04LF. Not much else is known, since no public datasheet is available.