IOP/Deckard

MIPS

I/O processor - MIPS R3000A (PS1 main processor) used in PS2 since SCPH-10000 to SCPH-700XX. Runs at a 36.864 MHz or a 33.8688 MHz (underclocked when in compatibility mode) clock speed. It is connected to an external 2 MB EDO-RAM chip. Later got replaced by a new IOP based around a PowerPC 405 core, but with an additional MIPS core.

Revisions

• 1.5 : CXD9553GB (GH-001, GH-003)
• 1.15: CXD9619GB (GH-004 - GH-014, GH-016)
• 2.0 : CXD9660GB (early GH-015)
• 2.1 : CXD9697GP (late GH-015, erroneously listed as "CXD9697GB" in service manuals?)
• 2.1 : CXD9732GP (very late GH-015, GH-017 - GH-022)
• 2.2 : CXD9783GP (GH-023)
• 2.4 : CXD9798GP (some GH-026 boards, maybe J-chassis GH-029?)
• 2.4 : CXD9799GP (PSX XPD-001/XPD-005, Namco System 256, some K-chassis slim boards, some GH-026 boards, maybe J-chassis GH-029?)
• 2.4 : CXD9799AGP (some K-chassis slim boards, Namco System 147, Namco System 148)

PowerPC

PowerPC 405 chip that replaced IOP and SPEED. It is connected to an external 4 MB DDR-SDRAM chip. In IOP emulator mode 2MB are used as a IOP memory. In PS2 used since SCPH-750XX model. New chip require some compatibility tweaks that are done per title by xparam file found in PS2 BOOTROM.

Note: There is some evidence that the new IOP additionally contain some kind of MIPS core connected thru AUX port.

Documentation More info

Revisions

• 3.0 : CXD9796GP (SCPH-750XX series/L-chassis)
  • As the only IOP revision to do so, this revision needs heatsinking!
• 3.0 : CXD9209GP (SCPH-770XX series/M-chassis)

Starting with N-chassis/SCPH-790XX, the IOP was integrated into the new main SoC together with its RAM. It still reports as version 3.0 in software.
Note: IOP revision (3.0) is taken from COP0 PRid which on models with PowerPC is actually emulated. So returned revision is just hardcoded value from DECKARD software IOP emulator file.

AUX Coprocessor

PowerPC series 4xx offer AUX port which functionality is similar to MIPS "COPx" solution. Not much is known about this component publicly. PS2 scene mentioned things like "Deckard SDK " or dumping bootrom for this chip. This suggest that chip was fully reverse engineered in private circle.

Opcodes Encoding

Guessed from assembly code, this section can be highly inaccurate.

Bits      Description

00...05 - PPC OP identificator (all 0 for aux)
06...10 - A = Destination register for result from aux
11...15 - B = Source register for arg to Aux
16...20 - C = Seems to be used as second arg register
21...27 - Function ?
28...29 - Unknown, always 1 is opcodes used by Deckard emulator
30...31 - Unknown, always 0 is opcodes used by Deckard emulator
                                  OP     A     B     C    func.  unk
For example, opcode 0x0003020C (000000 00000 00011 00000 0000010 1100) is used to set IOP/PS1 PC on Aux side using r3 PPC register as a source.