Editing SSBUS controller
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== Revisions == | == Revisions == | ||
"HDD Controller": | "HDD Controller": | ||
*1.2: CXD9546R (in DTL-T10000) | * 1.2: CXD9546R (in DTL-T10000) | ||
*2.0: CXD9566R (on all retail PCMCIA-motherboards: GH-001, GH-003, GH-008) | * 2.0: CXD9566R (on all retail PCMCIA-motherboards: GH-001, GH-003, GH-008) | ||
*3.0: CXD9611R (GH-004, GH-005, GH-006, GH-007, GH-010, GH-012, GH-013, GH-014) | * 3.0: CXD9611R (GH-004, GH-005, GH-006, GH-007, GH-010, GH-012, GH-013, GH-014) | ||
*3.1: CXD9611AR (GH-006, GH-007, GH-010, GH-012, GH-013, GH-014) | * 3.1: CXD9611AR (GH-006, GH-007, GH-010, GH-012, GH-013, GH-014) | ||
**Based on OKI MG73Q customer-structured array (at least some other revisions probably as well) | ** Based on OKI MG73Q customer-structured array (at least some other revisions probably as well) | ||
"SSBUS Controller": | "SSBUS Controller": | ||
* 3.1: CXD9611BR (GH-015(12-22), GH-015(31-41) | * 3.1: CXD9611BR (GH-015(12-22), GH-015(31-41), GH-017, GH-018, GH-019, GH-022, GH-023, XPD-001, XPD-005) | ||
*3.1: CXD9686AR ( | * 3.1: CXD9686AR (GH-022(31)) | ||
*3.1: CXD9686BR (GH-015(31-41)) | * 3.1: CXD9686BR (GH-015(31-41)) | ||
*3.1: CXD9686R ( | * 3.1: CXD9686R (GH-017, GH-019) | ||
*3.2: CXD2955R (GH-026, GH-027, GH-029, GH-032, GH-035) | * 3.2: CXD2955R (GH-026, GH-027, GH-029, GH-032, GH-035) | ||
**Additionally also includes functionality of [[SPU2]] | ** Additionally also includes functionality of [[SPU2]] | ||
Starting with GH-026, the SSBUS controller and the [[SPU2]] were combined into a single chip (CXD2955R), until the SSBUS controller ultimately became obsolete with the introduction of the L-chassis (SCPH- | Starting with GH-026, the SSBUS controller and the [[SPU2]] were combined into a single chip (CXD2955R), until the SSBUS controller ultimately became obsolete with the introduction of the L-chassis (SCPH-75XXX). From a software viewpoint, these newer consoles report a v3.1 SSBUS controller. | ||