Editing SPU2
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Sound processor of the PS2. Is connected to or contains (depending on revision) 2 MB of EDO-RAM. | Sound processor of the PS2. Is connected to or contains (depending on revision) 2 MB of EDO-RAM. | ||
Current versions of PS2ident misidentify some of these, e.g. CXD2942AR | Current versions of PS2ident misidentify some of these, e.g. CXD2942AR/CXD2950R will be identified as a non-existent CXD2947AR. | ||
To do - What about GH-016? | |||
== Revisions == | == Revisions == | ||
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** [[File:6dg0Nsh.jpg|200px]] | ** [[File:6dg0Nsh.jpg|200px]] | ||
* CXD2942BR (GH-010, GH-012, GH-013, GH-014) | * CXD2942BR (GH-010, GH-012, GH-013, GH-014) | ||
* CXD2950R ( | * CXD2950R (GH-015) | ||
* CXD2947R (GH-017, GH-018, GH-019, GH-022, GH-023, GH-036, GH-037, GH-040, GH-041, GH-051, GH-052, XPD-001, XPD-005) | * CXD2947R (GH-017, GH-018, GH-019, GH-022, GH-023, GH-036, GH-037, GH-040, GH-041, GH-051, GH-052, XPD-001, XPD-005) | ||
** SPU2-RAM moved into SPU2 itself; no external SPU2-RAM | ** SPU2-RAM moved into SPU2 itself; no external SPU2-RAM | ||
* CXD2955R (GH-026, GH-027, GH-029, GH-032, GH-035) | * CXD2955R (GH-026, GH-027, GH-029, GH-032, GH-035) | ||
** Additionally also includes functionality of [[ | ** Additionally also includes functionality of [[SSBUS controller]] | ||
Starting with GH-026, the SSBUS controller and the SPU2 were combined into a single chip (CXD2955R), until the SSBUS controller functionality ultimately became obsolete with the introduction of the L-chassis (SCPH-750XX, GH-036 and newer), hence the switch way back to CXD2947R that was introduced with GH-017. | |||
Starting with GH-061, the SPU2 was integrated into the new main SoC ([[Emotion Engine#Revisions|CXD2976GB]]) and does not exist as a dedicated IC anymore. | Starting with GH-061, the SPU2 was integrated into the new main SoC ([[Emotion Engine#Revisions|CXD2976GB]]) and does not exist as a dedicated IC anymore. | ||