Editing SPU2
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== Overview == | == Overview == | ||
Sound processor of the PS2. Is connected to or contains (depending on revision) 2 MB of EDO-RAM | Sound processor of the PS2. Is connected to or contains (depending on revision) 2 MB of EDO-RAM. | ||
== Revisions == | == Revisions == | ||
* CXD2942R (GH-001, GH-003, GH-008) | * CXD2942R (GH-001, GH-003, GH-008) | ||
* CXD2942AR (GH-004, GH-005, GH-006, GH-007 | * CXD2942AR (GH-004, GH-005, GH-006, GH-007, GH-010, GH-012, GH-013, GH-014) | ||
** [[File:6dg0Nsh.jpg|200px]] | ** [[File:6dg0Nsh.jpg|200px]] | ||
* CXD2942BR (GH-010, GH-012, GH-013, GH-014) | * CXD2942BR (GH-010, GH-012, GH-013, GH-014) | ||
* CXD2950R ( | * CXD2950R (GH-015) | ||
* CXD2947R (GH-017, GH-018, GH-019, GH-022, GH-023, GH-036, GH-037, GH-040, GH-041, GH-051, GH-052, XPD-001, XPD-005) | * CXD2947R (GH-017, GH-018, GH-019, GH-022, GH-023, GH-036, GH-037, GH-040, GH-041, GH-051, GH-052, XPD-001, XPD-005) | ||
** SPU2-RAM moved into SPU2 itself; no external SPU2-RAM | ** SPU2-RAM moved into SPU2 itself; no external SPU2-RAM | ||
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** Additionally also includes functionality of [[SSBUS controller]] | ** Additionally also includes functionality of [[SSBUS controller]] | ||
Starting with GH-026, the SSBUS controller and the SPU2 were combined into a single chip (CXD2955R), until the SSBUS controller functionality ultimately became obsolete with the introduction of the L-chassis (SCPH- | Starting with GH-026, the SSBUS controller and the SPU2 were combined into a single chip (CXD2955R), until the SSBUS controller functionality ultimately became obsolete with the introduction of the L-chassis (SCPH-75XXX, GH-036 and newer), hence the move back to CXD2947R on GH-036 and newer. | ||
Starting with GH-061, the SPU2 was integrated into the new main SoC ([[Emotion Engine#Revisions|CXD2976GB]]) and does not exist as a dedicated IC anymore. | Starting with GH-061, the SPU2 was integrated into the new main SoC ([[Emotion Engine#Revisions|CXD2976GB]]) and does not exist as a dedicated IC anymore. | ||