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=== Revisions ===
=== Revisions ===
* 1.5 : CXD9553GB  (GH-001, GH-003)
* 1.5 : CXD9553GB  (GH-001, GH-003)
* ??? : CXD9590GB  (MPU-4 in DTL-T10000H)
* 1.15: CXD9619GB  (GH-004 - GH-014, GH-016)
* 1.15: CXD9619GB  (GH-004 - GH-014, GH-016)
* 2.0 : CXD9660GB  (early GH-015)
* 2.0 : CXD9660GB  (early GH-015)
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* 2.1 : CXD9732GP  (very late GH-015, GH-017 - GH-022)
* 2.1 : CXD9732GP  (very late GH-015, GH-017 - GH-022)
* 2.2 : CXD9783GP  (GH-023)
* 2.2 : CXD9783GP  (GH-023)
* 2.4 : CXD9798GP  (some GH-026 boards, some GH-029 boards)
* 2.4 : CXD9798GP  (some GH-026 boards, maybe J-chassis GH-029?)
* 2.4 : CXD9799GP  (PSX XPD-001/XPD-005, some Namco System 256, some K-chassis slim boards, some GH-026 boards, maybe J-chassis GH-029?)
* 2.4 : CXD9799GP  (PSX XPD-001/XPD-005, Namco System 256, some K-chassis slim boards, some GH-026 boards, maybe J-chassis GH-029?)
* 2.4 : CXD9799AGP (some Namco System 256, some K-chassis slim boards, Namco System 147, Namco System 148)
* 2.4 : CXD9799AGP (some K-chassis slim boards, Namco System 147, Namco System 148)


==PowerPC==
==PowerPC==
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If these lookup tables get relocated,  up to 966kb of free RAM can be obtained without breaking the DECKARD emulator.
If these lookup tables get relocated,  up to 966kb of free RAM can be obtained without breaking the DECKARD emulator.


Note: There is some support hardware inside the PPC IOP for the emulation. It's not purely software emulation.
Note: There is some evidence that the new IOP additionally contain some kind of MIPS core connected thru AUX port.


[https://www2.informatik.hu-berlin.de/~fwinkler/psvfpga/amirix/405_um.pdf Documentation]
[https://www2.informatik.hu-berlin.de/~fwinkler/psvfpga/amirix/405_um.pdf Documentation]
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===Compatibility modes===
===Compatibility modes===
The addition of this PPC CPU required some compatibility modes added. They're enabled/disabled by the rom0:XPARAM IRX module. The console had a database of games that needed compatibility modes, rom0:PS2LOGO was in charge of looking at this database and applying the patches. Games were also capable of providing compatibility modes on their own by adding a '''PARAM2''' field on their system.cnf file. Wich consisted on the XPARAM config value followed by an MD5 checksum for integrity checks (to avoid applying the XPARAM if the data was corrupted).
The addition of this PPC CPU required some compatibility modes added. They're enabled/disabled by the rom0:XPARAM IRX module. The console had a database of games that needed compatibility modes, rom0:PS2LOGO was in charge of looking at this database and applying the patches. Games were also capable of providing compatibility modes on their own by adding a '''PARAM2''' field on their system.cnf file. Wich consisted on the XPARAM config value followed by an MD5 checksum for integrity checks (to avoid applying the XPARAM if the data was corrupted).
There were only found two revisions of this compatibility mode database, one included on SCPH-750xx, and the second one was used on SCPH-770xx and never got updated again.
There were only found two revisions of this compatibility mode database, one included on SCPH-75xxx, and the second one was used on SCPH-77xxx and never got updated again.


Information about this database and the actual databases can be found on some notes that got recently added to the [https://github.com/ps2homebrew/Open-PS2-Loader/tree/master/notes/xparam OpenPS2Loader repository]
Information about this database and the actual databases can be found on some notes that got recently added to the [https://github.com/ps2homebrew/Open-PS2-Loader/tree/master/notes/xparam OpenPS2Loader repository]
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=== Revisions ===
=== Revisions ===
* 3.0 : CXD9796GP (SCPH-750XX series/L-chassis)
* 3.0 : CXD9796GP (SCPH-750XX series/L-chassis)
**As the only IOP revision to do so, '''this revision needs heatsinking!'''
** As the only IOP revision to do so, '''this revision needs heatsinking!'''
*3.0 : CXD9209GP (SCPH-770XX series/M-chassis)
* 3.0 : CXD9209GP (SCPH-770XX series/M-chassis)


Starting with N-chassis/SCPH-790XX, the IOP was integrated into the new main SoC ([[Emotion Engine#Revisions|CXD2976GB]]) together with its RAM. It still reports as version 3.0 in software.
Starting with N-chassis/SCPH-790XX, the IOP was integrated into the new main SoC together with its RAM. It still reports as version 3.0 in software.
<br>Note: IOP revision (3.0) is taken from COP0 PRid which on models with PowerPC is actually emulated. So returned revision is just hardcoded value from DECKARD software IOP emulator file.
<br>Note: IOP revision (3.0) is taken from COP0 PRid which on models with PowerPC is actually emulated. So returned revision is just hardcoded value from DECKARD software IOP emulator file.


although the DECKARD emulator reports different compilation dates across different slim models (compilation date is printed at emulator startup over it's UART), it seems Sony never updated the emulator, just recompiled it.
although the DECKARD emulator reports different compilation dates across different slim models (compilation date is printed at emulator startup over it's UART), it seems Sony never updated the emulator, just recompiled it.


=== UART ===
=== AUX Coprocessor ===
The PowerPC CPU also had an UART. Unlike the EE UART, Sony had no actual use for it, so the pads aren't even tinned.
PowerPC series 4xx offer AUX port which functionality is similar to MIPS "COPx" solution. Not much is known about this component publicly. PS2 scene mentioned things like "[https://www.psx-place.com/threads/eject-tray-elf.19072/page-2#post-216993 Deckard SDK ]" or dumping bootrom for this chip. This suggest that chip was fully reverse engineered in private circle.


The signals use 3.5V logic levels and baud rate of 57600 bps
==== Opcodes Encoding ====
 
[[File:PPC-UART.png|200px]]
 
=== AUX Coprocessor===
PowerPC series 4xx offer AUX port which functionality is similar to MIPS "COPx" solution. Not much is known about this component publicly. PS2 scene mentioned things like "[https://www.psx-place.com/threads/eject-tray-elf.19072/page-2#post-216993 Deckard SDK] " or dumping bootrom for this chip. This suggest that chip was fully reverse engineered in private circle.
 
====Opcodes Encoding====
Guessed from assembly code, this section can be highly inaccurate.
Guessed from assembly code, this section can be highly inaccurate.


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