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==MIPS==
==MIPS==


I/O processor - MIPS R3000A (PS1 main processor) used in PS2 since SCPH-10000 to SCPH-700XX. Runs at a 36.864 MHz or a 33.8688 MHz (underclocked when in compatibility mode) clock speed. It is connected to an external 2 MB EDO-RAM chip. Later got replaced by a new IOP based around a PowerPC 405 core, but with an additional MIPS core.
I/O processor - MIPS R3000A (PS1 main processor) used in PS2 since SCPH-10000 to SCPH-700XX. Runs at a 36.864 mHz clock speed. It is connected to an external 2 MB EDO-RAM chip. Later got replaced by a new IOP based around a PowerPC 405 core, but with an additional MIPS core.


=== Revisions ===
=== Revisions ===
* 1.5 : CXD9553GB  (GH-001, GH-003)
* 1.5 : CXD9553GB  (GH-001, GH-003)
* ??? : CXD9590GB  (MPU-4 in DTL-T10000H)
* 1.15: CXD9619GB  (GH-004 - GH-014, GH-016)
* 1.15: CXD9619GB  (GH-004 - GH-014, GH-016)
* 2.0 : CXD9660GB  (early GH-015)
* 2.0 : CXD9660GB  (earlier GH-015)
* 2.1 : CXD9697GP  (late GH-015, erroneously listed as "CXD9697GB" in service manuals?)
* 2.1 : CXD9697GP  (later GH-015, erroneously listed as "CXD9697GB" in service manuals?)
* 2.1 : CXD9732GP  (very late GH-015, GH-017 - GH-022)
* 2.1 : CXD9732GP  (GH-017 - GH-022)
* 2.2 : CXD9783GP  (GH-023)
* 2.2 : CXD9783GP  (GH-023)
* 2.4 : CXD9798GP  (some GH-026 boards, some GH-029 boards)
* 2.4 : CXD9798GP  (some GH-026 boards, maybe J-chassis GH-029?)
* 2.4 : CXD9799GP  (PSX XPD-001/XPD-005, some Namco System 256, some K-chassis slim boards, some GH-026 boards, maybe J-chassis GH-029?)
* 2.4 : CXD9799GP  (PSX XPD-001/XPD-005, Namco System 256, some K-chassis slim boards, some GH-026 boards, maybe J-chassis GH-029?)
* 2.4 : CXD9799AGP (some Namco System 256, some K-chassis slim boards, Namco System 147, Namco System 148)
* 2.4 : CXD9799AGP (some K-chassis slim boards, Namco System 147, Namco System 148)


==PowerPC==
==PowerPC==


PowerPC 405 chip that replaced IOP and [[SPEED]] since SCPH-750XX model. It is connected to an external 4 MB DDR-SDRAM chip. The first 2Mb were reserved to be used as the RAM of the emulated IOP, the other 2Mb are used by the DECKARD emulator, however, between the emulator itself and some lookup tables found on RAM, it doesn't consume all available RAM.
PowerPC 405 chip that replaced IOP and [[SPEED]]. It is connected to an external 4 MB DDR-SDRAM chip. In IOP emulator mode 2MB are used as a IOP memory. In PS2 used since SCPH-750XX model. New chip require some compatibility tweaks that are done per title by xparam file found in PS2 BOOTROM.
If these lookup tables get relocated,  up to 966kb of free RAM can be obtained without breaking the DECKARD emulator.


Note: There is some support hardware inside the PPC IOP for the emulation. It's not purely software emulation.
Note: There is some evidence that the new IOP additionally contain some kind of MIPS core connected thru AUX port.


[https://www2.informatik.hu-berlin.de/~fwinkler/psvfpga/amirix/405_um.pdf Documentation]
[https://www2.informatik.hu-berlin.de/~fwinkler/psvfpga/amirix/405_um.pdf Documentation]
[http://psx-scene.com/forums/f19/deckard-ppc-iop-discussion-157416/#post1215298 More info]
[http://psx-scene.com/forums/f19/deckard-ppc-iop-discussion-157416/#post1215298 More info]
PPC monitor, a homebrew application that runs on this CPU, has some documentation about it, how it works and how to run code on it along the DECKARD emulator.
https://israpps.github.io/PPC-Monitor/
===Compatibility modes===
The addition of this PPC CPU required some compatibility modes added. They're enabled/disabled by the rom0:XPARAM IRX module. The console had a database of games that needed compatibility modes, rom0:PS2LOGO was in charge of looking at this database and applying the patches. Games were also capable of providing compatibility modes on their own by adding a '''PARAM2''' field on their system.cnf file. Wich consisted on the XPARAM config value followed by an MD5 checksum for integrity checks (to avoid applying the XPARAM if the data was corrupted).
There were only found two revisions of this compatibility mode database, one included on SCPH-750xx, and the second one was used on SCPH-770xx and never got updated again.
Information about this database and the actual databases can be found on some notes that got recently added to the [https://github.com/ps2homebrew/Open-PS2-Loader/tree/master/notes/xparam OpenPS2Loader repository]


=== Revisions ===
=== Revisions ===
* 3.0 : CXD9796GP (SCPH-750XX series/L-chassis)
* 3.0 : CXD9796GP (SCPH-750XX series/L-chassis)
**As the only IOP revision to do so, '''this revision needs heatsinking!'''
** As the only IOP revision to do so, '''this revision needs heatsinking!'''
*3.0 : CXD9209GP (SCPH-770XX series/M-chassis)
* 3.0 : CXD9209GP (SCPH-770XX series/M-chassis)
 
Starting with N-chassis/SCPH-790XX, the IOP was integrated into the new main SoC ([[Emotion Engine#Revisions|CXD2976GB]]) together with its RAM. It still reports as version 3.0 in software.
<br>Note: IOP revision (3.0) is taken from COP0 PRid which on models with PowerPC is actually emulated. So returned revision is just hardcoded value from DECKARD software IOP emulator file.
 
although the DECKARD emulator reports different compilation dates across different slim models (compilation date is printed at emulator startup over it's UART), it seems Sony never updated the emulator, just recompiled it.
 
=== UART ===
The PowerPC CPU also had an UART. Unlike the EE UART, Sony had no actual use for it, so the pads aren't even tinned.
 
The signals use 3.5V logic levels and baud rate of 57600 bps
 
[[File:PPC-UART.png|200px]]
 
=== AUX Coprocessor===
PowerPC series 4xx offer AUX port which functionality is similar to MIPS "COPx" solution. Not much is known about this component publicly. PS2 scene mentioned things like "[https://www.psx-place.com/threads/eject-tray-elf.19072/page-2#post-216993 Deckard SDK] " or dumping bootrom for this chip. This suggest that chip was fully reverse engineered in private circle.
 
====Opcodes Encoding====
Guessed from assembly code, this section can be highly inaccurate.


Bits      Description
Starting with N-chassis/SCPH-790XX, the IOP was integrated into the new main SoC together with its RAM. It still reports as version 3.0 in software.
00...05 - PPC OP identificator (all 0 for aux)
06...10 - A = Destination register for result from aux
11...15 - B = Source register for arg to Aux
16...20 - C = Seems to be used as second arg register
21...27 - Function ?
28...29 - Unknown, always 1 is opcodes used by Deckard emulator
30...31 - Unknown, always 0 is opcodes used by Deckard emulator
                                  OP    A    B    C    func.  unk
For example, opcode 0x0003020C (000000 00000 00011 00000 0000010 1100) is used to set IOP/PS1 PC on Aux side using r3 PPC register as a source.
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