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===DRCG-lite #2===
===DRCG-lite #2===
''This additional DRCG is not found on boards from the same chassis types that use the second revision GS (CXD2944GB) (GH-004, GH-006, GH-008, GH-010, GH-013).''
Additionally, all boards that have the original [[Graphics_Synthesizer|GS]] with metal heat spreader, CXD2934GB (GH-001, GH-003, GH-005, GH-007, GH-012, GH-014, GH-016), have a second DRCG-lite IC (also with an 18.432 Mhz XTAL) which is set to a multiplier of 16 to generate a 294.912 Mhz clock which is fed into GS. ''This additional DRCG is not found on their same-chassis-counterparts (GH-004, GH-006, GH-008, GH-010, GH-013) that use the second revision GS (CXD2944GB).''


All boards that have the original [[Graphics_Synthesizer|GS]] with metal heat spreader, CXD2934GB (GH-001, GH-003, GH-005, GH-007, GH-012, GH-014, GH-016), have a second DRCG-lite IC (also with an 18.432 Mhz XTAL) which is set to a multiplier of 16 to generate a 294.912 Mhz clock which is fed into GS.
= F, G, H chassis =
= F, G, H chassis =
Based around one "DRCG-lite" and one "GMCG" (=Graphics Media Clock Generator, e.g. Cypress CY24141) clock generator.  
Based around one "DRCG-lite" and one "GMCG" (=Graphics Media Clock Generator, e.g. Cypress CY24141) clock generator.  


===GMCG===
===GMCG===
The GMCG has a 18.432 Mhz XTAL and generates a 54 Mhz or 53.9 Mhz clock for GS (selection between 54 and 53.9 is done via control line from [[DEV9C]], later from the SPU2+DEV9C-Controller combo IC) and also creates a 18.432 Mhz input clock for the DRCG-lite.  
The GMCG has a 18.432 Mhz XTAL and generates a 54 Mhz or 53.9 Mhz clock for GS (selection between 54 and 53.9 is done via control line from [[SSBUS controller]], later from the SPU2+SSBUS-Controller combo IC) and also creates a 18.432 Mhz input clock for the DRCG-lite.  


===DRCG-lite===
===DRCG-lite===
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